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ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 1 ? 2009-2011 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. virtex-5q fpga electrical characteristics defense-grade virtex?-5q fpgas are available in -2i, -1i, and -1m (only fx70t and fx100t devices in -1m) speed grades, with -2i having the highest performance. virtex-5q fpga dc and ac characteristics are specified for the industrial temperature range. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. this virtex-5q fpga data sheet, part of an overall set of documentation on the virtex-5 family of fpgas, is available on the xilinx website: ? ds174 , virtex-5q family overview ? ug190 , virtex-5 fpga user guide ? ug191 , virtex-5 fpga configuration guide ? ug192 , virtex-5 fpga system monitor user guide ? ug193 , virtex-5 fpga xtremedsp? design considerations user guide ? ug194 , virtex-5 fpga embedded tri-mode ethernet mac user guide ? ug195 , virtex-5 fpga packaging and pinout specification ? ug196 , virtex-5 fpga rocketio? gtp transceiver user guide ? ug197 , virtex-5 fpga integrated endpoint block user guide for pci express? designs ? ug198 , virtex-5 fpga rocketio gtx transceiver user guide ? ug200 , embedded processor block in virtex-5 fpgas reference guide ? ug203 , virtex-5 fpga pcb designer?s guide all specifications are subject to change without notice. virtex-5q fpga dc characteristics 74 virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 product specification ta bl e 1 : absolute maximum ratings (1) symbol description range units v ccint internal supply voltage relative to gnd ?0.5 to 1.1 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.0 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.75 v v batt key memory battery backup supply ?0.5 to 4.05 v v ref input reference voltage ?0.5 to 3.75 v v in (3) 3.3v i/o input voltage relative to gnd (2) (user and dedicated i/os) ?0.75 to 4.05 v 3.3v i/o input voltage relative to gnd (restricted to maximu m of 100 user i/os) (4) ?0.85 to 4.3 (industrial temperature) v 2.5v or below i/o input voltage relative to gnd (user and dedicated i/os) ?0.75 to v cco +0.5 v i in current applied to an i/o pin, powered or unpowered 100 ma total current applied to all i/o pins, powered or unpowered 100 ma v ts voltage applied to 3-state 3.3v output (2) (user and dedicated i/os) ?0.75 to 4.05 v voltage applied to 3-state 2.5v or below ou tput (user and dedicated i/os) ?0.75 to v cco +0.5 v t stg storage temperature (ambient) ?65 to 150 c
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 2 t sol maximum soldering temperature (5) +220 c t j maximum junction temperature (5) + 125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. for 3.3v i/o operation, refer to virtex-5 fpga user guide , chapter 6, 3.3v i/o design guidelines. 3. 3.3v i/o absolute maximum limit applied to dc and ac signals. 4. for more flexibility in specific designs, a maximum of 100 user i/os can be stressed beyond the normal specification for no m ore than 20% of a data period. 5. for soldering guidelines, refer to ug112 : device package user guide . for thermal considerations, refer to ug195 : virtex-5 fpga packaging and pinout specification on the xilinx website. ta bl e 2 : recommended operating conditions symbol description temperature range min max units v ccint internal supply voltage relative to gnd, t j = ?40c to +100c industrial 0.95 1.05 v v ccaux (1) auxiliary supply voltage relative to gnd, t j = ?40c to +100c industrial 2.375 2.625 v v cco (2)(3)(4) supply voltage relative to gnd, t j = ?40c to +100c industrial 1.14 3.45 v v in 3.3v supply voltage relative to gnd, t j = ?40c to +100c industrial gnd ? 0.20 3.45 v 2.5v and below supply voltage relative to gnd, t j = ?40c to +100c industrial gnd ? 0.20 v cco +0.2 v i in maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. industrial 10 ma v batt (5) battery voltage relative to gnd, t j = ?40c to +100c industrial 1.0 3.6 v notes: 1. recommended maximum voltage drop for v ccaux is 10 mv/ms. 2. configuration data is retained even if v cco drops to 0v. 3. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. 4. the configuration supply voltage v cc_config is also known as v cco_0 . 5. v batt is required only when using bitstream encryption. if battery is not used, connect v batt to either ground or v ccaux . ta bl e 3 : dc characteristics over recommended operating conditions symbol description min typ max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 v v dri data retention v ccaux voltage (below which configuration data might be lost) 2.0 v i ref v ref leakage current per pin 10 a i l input or output leakage current per pin (sample-tested) 10 a c in input capacitance (sample-tested) 8pf i rpu (1) pad pull-up (when selected) @ v in =0v, v cco = 3.3v 20 150 a pad pull-up (when selected) @ v in =0v, v cco =2.5v 10 90 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 5 45 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 3 30 a pad pull-up (when selected) @ v in =0v, v cco = 1.2v 2 15 a i rpd (1) pad pull-down (when selected) @ v in = 2.5v 5 110 a i batt (2) battery supply current 150 na n temperature diode ideality factor 1.0002 n r series resistance 5.0 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. maximum value specified for worst case process at 25c. ta bl e 1 : absolute maximum ratings (1) (cont?d) symbol description range units
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 3 important note typical values for quiescent supply current are now spec ified at nominal voltage, 85c junction temperatures (t j ). xilinx recommends analyzing static power consumption at t j = 85c because the majority of designs operate near the high end of the commercial temperature range. data sheets for older produc ts (e.g., virtex-4 devices) st ill specify typical quiescent supply current at t j = 25c. quiescent supply current is specified by speed grade for virtex-5q devices. use the xpower estimator (xpe) spreadsh eet tool (download at www.xilinx.com/power ) to calculate static power consumption for conditions other than those specified in ta b l e 4 . ta bl e 4 : typical quiescent supply current symbol description device speed and temperature grade units -2 (i) -1 (i) -1 (m) i ccintq quiescent v ccint supply current xq5vlx30t 507 317 n/a ma xq5vlx85 1072 833 n/a ma xq5vlx110 1391 1109 n/a ma xq5vlx110t 1448 1154 n/a ma xq5vlx155t 2674 2188 n/a ma xq5vlx220t 2844 2328 n/a ma xq5vlx330t n/a 3492 n/a ma xq5vsx50t 1092 840 n/a ma xq5vsx95t 1924 1475 n/a ma xq5vsx240t n/a 3168 n/a ma xq5vfx70t 1658 1658 1658 ma xq5vfx100t 2875 2875 2875 ma xq5vfx130t 3041 3041 n/a ma xq5vfx200t n/a 3755 n/a ma i ccoq quiescent v cco supply current xq5vlx30t 1.5 1.5 n/a ma xq5vlx85 3 3 n/a ma xq5vlx110 4 4 n/a ma xq5vlx110t 4 4 n/a ma xq5vlx155t 8 8 n/a ma xq5vlx220t 8 8 n/a ma xq5vlx330t n/a 12 n/a ma xq5vsx50t 2 2 n/a ma xq5vsx95t 4 4 n/a ma xq5vsx240t n/a 12 n/a ma xq5vfx70t666ma xq5vfx100t 7 7 7 ma xq5vfx130t 8 8 n/a ma xq5vfx200t n/a 10 n/a ma
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 4 i ccauxq quiescent v ccaux supply current xq5vlx30t 43 43 n/a ma xq5vlx85 93 93 n/a ma xq5vlx110 125 125 n/a ma xq5vlx110t 130 130 n/a ma xq5vlx155t 177 177 n/a ma xq5vlx220t 236 236 n/a ma xq5vlx330t n/a 353 n/a ma xq5vsx50t 74 74 n/a ma xq5vsx95t 131 131 n/a ma xq5vsx240t n/a 300 n/a ma xq5vfx70t 110 110 110 ma xq5vfx100t 150 150 150 ma xq5vfx130t 180 180 n/a ma xq5vfx200t n/a 250 n/a ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (t j ). industrial (i) and military (m) grade devices have the same typical values as commercial (c) grade devices at 85c, but higher values at 100c (i) and 125c (m). use the xpe/xpa powe r tools to calculate values for conditions other than specified in this data sheet. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. if dci or differential signaling is used, more accurate quiescent current estimates can be obtained by using the xpower estim ator (xpe) or xpower analyzer (xpa) tools. ta bl e 4 : typical quiescent supply current (cont?d) symbol description device speed and temperature grade units -2 (i) -1 (i) -1 (m)
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 5 power-on power supply requirements xilinx fpgas require a certain amount of supply current during power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. the power supplies can be turned on in any sequence, though the specifications shown in ta b l e 5 are for the recommended power-on sequence of v ccint , v ccaux , and v cco . the i/o will remain 3-stated through power-on if the recommended power-on sequence is followed. xilinx does not specify the current or i/o behavior for other power-on sequences. ta bl e 5 shows the minimum current required by virtex-5q devices for proper power-on and configuration. if the current minimums shown in ta b l e 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. the fpga must be configured after v ccint is applied. once initialized and configured, use the xpower tools to estimate current drain on these supplies. ta b l e 5 : power-on current for virtex-5q devices device i ccintmin i ccauxmin i ccomin units typ (1) typ (1) typ (1) xq5vlx30t 246 86 50 ma xq5vlx85 492 186 100 ma xq5vlx110 623 250 100 ma xq5vlx110t 651 260 100 ma xq5vlx155t 728 368 100 ma xq5vlx220t 1056 472 150 ma xq5vlx330t 1509 706 150 ma xq5vsx50t 472 148 50 ma xq5vsx95t 804 262 100 ma xq5vsx240t 1632 662 150 ma xq5vfx70t 695 232 100 ma xq5vfx100t 749 298 100 ma xq5vfx130t 1111 392 150 ma xq5vfx200t 1222 534 150 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. the maximum startup current can be obtained using the xpower estimator (xpe) or xpower analyzer (xpa) tools and adding the quiescent plus dynamic current consumption. ta bl e 6 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage re lative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage rela tive to gnd 0.20 to 50.0 ms
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 6 selectio? dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 7 : selectio dc input and output levels i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl ?0.3 0.8 2.0 3.45 0.4 2.4 note 3 note 3 lvcmos33, lvdci33 ?0.3 0.8 2.0 3.45 0.4 v cco ? 0.4 note 3 note 3 lvcmos25, lvdci25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ? 0.4 note 3 note 3 lvcmos18, lvdci18 ?0.3 35% v cco 65% v cco v cco + 0.3 0.45 v cco ? 0.45 note 4 note 4 lvcmos15, lvdci15 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note 4 note 4 lvcmos12 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note 6 note 6 pci33_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco note 5 note 5 pci66_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco note 5 note 5 pci-x (5) ?0.2 35% v cco 50% v cco v cco 10% v cco 90% v cco note 5 note 5 gtlp ?0.3 v ref ?0.1 v ref +0.1 ? 0.6 ? 36 ? gtl ?0.3 v ref ?0.05 v ref +0.05 ? 0.4 ? 32 ? hstl i_12 ?0.3 v ref ?0.1 v ref +0.1 v cco + 0.3 25% v cco 75% v cco 6.3 6.3 hstl i (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 16 ?16 hstl iii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 24 ?8 hstl iv (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 48 ?8 diff hstl i (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? diff hstl ii (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? sstl2 i ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2 ii ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.81 v tt + 0.81 16.2 ?16.2 diff sstl2 i ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? diff sstl2 ii ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? sstl18 i ?0.3 v ref ? 0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18 ii ?0.3 v ref ? 0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 i ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? notes: 1. tested according to relevant specifications. 2. applies to both 1.5v and 1.8v hstl. 3. using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 4. using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 5. for more information on pci33_3, pci66_3, and pci-x, refer to virtex-5 fpga user guide, chapter 6, 3.3v i/o design guidelines . 6. supported drive strengths of 2, 4, 6, or 8 ma.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 7 ht dc specifications (ht_25) lvds dc specifications (lvds_25) extended lvds dc specif ications (lvdsext_25) ta bl e 8 : ht dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v od differential output voltage r t = 100 ? across q and q signals 495 600 840 mv ? v od change in v od magnitude ?15 15 mv v ocm output common mode voltage r t = 100 ? across q and q signals 495 600 715 mv ? v ocm change in v ocm magnitude ?15 15 mv v id input differential voltage 200 600 1000 mv ? v id change in v id magnitude ?15 15 mv v icm input common mode voltage 440 600 780 mv ? v icm change in v icm magnitude ?15 15 mv ta bl e 9 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 ? across q and q signals 1.675 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.825 v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 ? across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.125 1.250 1.375 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 2.2 v ta bl e 1 0 : extended lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 ? across q and q signals ? 1.785 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.715 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 ? across q and q signals 350 ? 820 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.025 1.250 1.475 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high common-mode input voltage = 1.25v 100 ? 1000 mv v icm input common-mode voltage differential input voltage = 350 mv 0.3 1.2 2.2 v
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 8 lvpecl dc specifi cations (lvpecl_25) these values are valid when driving a 100 ? differential load only, i.e., a 100 ? resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are co mpatible with devices toler ant of lower common-mode ranges. ta b l e 1 1 summarizes the dc output specif ications of lvpecl. for more information on using lvpecl , see virtex-5 fpga user guide, chapter 6, selectio resources . powerpc 440 switchin g characteristics consult the embedded processor block in virtex-5 fpgas reference guide for further information. ta bl e 1 1 : lvpecl dc specifications symbol dc parameter min typ max units v oh output high voltage v cc ? 1.025 1.545 v cc ?0.88 v v ol output low voltage v cc ? 1.81 0.795 v cc ?1.62 v v icm input common-mode voltage 0.6 2.2 v v idiff differential input voltage (1)(2) 0.100 1.5 v notes: 1. recommended input maximum voltage not to exceed v ccaux +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 1 2 : processor block switching characteristics clock name description speed grade units -2i -1i -1m cpmc440clk cpu clock 475 400 400 mhz cpminterconnectclk xbar clock 316.6 266.6 266.6 mhz cpmppcs0plbclk slave 0 plb clock (1) 158.3 133.3 133.3 mhz cpmppcs1plbclk slave 1 plb clock (1) 158.3 133.3 133.3 mhz cpmppcmplbclk master plb clock (1) 158.3 133.3 133.3 mhz cpmmcclk memory interface clock (1)(2) 316.6 266.6 266.6 mhz cpmfcmclk fcm clock (1) 237.5 200 200 mhz cpmdcrclk fpga logic dcr clock (1) 158.3 133.3 133.3 mhz cpmdma0llclk dma0 ll clock (1) 250 200 200 mhz cpmdma1llclk dma1 ll clock (1) 250 200 200 mhz cpmdma2llclk dma2 ll clock (1) 250 200 200 mhz cpmdma3llclk dma3 ll clock (1) 250 200 200 mhz jtgc440tck jtag clock 50 50 50 mhz cpmc440timerclock timer clock 237.5 200 200 mhz notes: 1. typical bus frequencies are provided for reference only, actual frequencies are user-design dependent. 2. refer to ds567 , ddr2 memory controller for powerpc 440 processors , for maximum clock speed of designs using the ddr2 memory controller for powerpc? 440 processors.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 9 ta bl e 1 3 : processor block mib switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmmcclk 1.247 1.463 1.463 ps t ck_address cpmmcclk 1.136 1.38 1.38 ps t ck_data cpmmcclk 1.172 1.38 1.38 ps t control_ck cpmmcclk 0.844 0.941 0.941 ps t data_ck cpmmcclk 0.95 1.058 1.058 ps ta bl e 1 4 : processor block plbm sw itching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmppcmplbclk 1.095 1.354 1.354 ps t ck_address cpmppcmplbclk 1.372 1.673 1.673 ps t ck_data cpmppcmplbclk 1.257 1.535 1.535 ps t control_ck cpmppcmplbclk 1.79 1.86 1.86 ps t data_ck cpmppcmplbclk 0.914 1.059 1.059 ps ta bl e 1 5 : processor block plbs0 switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmppcs0plbclk 1.196 1.462 1.462 ps t ck_data cpmppcs0plbclk 1.189 1.461 1.461 ps t control_ck cpmppcs0plbclk 1.545 1.836 1.836 ps t address_ck cpmppcs0plbclk 1.492 1.787 1.787 ps t data_ck cpmppcs0plbclk 0.971 1.124 1.124 ps ta bl e 1 6 : processor block plbs1 switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmppcs1plbclk 1.234 1.525 1.525 ps t ck_data cpmppcs1plbclk 1.298 1.615 1.615 ps t control_ck cpmppcs1plbclk 1.596 1.921 1.921 ps t address_ck cpmppcs1plbclk 1.568 1.864 1.864 ps t data_ck cpmppcs1plbclk 0.969 1.127 1.127 ps
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 10 ta bl e 1 7 : processor block dma0 switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmdma0llclk 1.42 1.665 1.665 ps t ck_data cpmdma0llclk 1.472 1.712 1.712 ps t control_ck cpmdma0llclk 0.558 0.716 0.716 ps t data_ck cpmdma0llclk ?0.105 ?0.104 ?0.104 ps ta bl e 1 8 : processor block dma1 switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmdma1llclk 1.266 1.474 1.474 ps t ck_data cpmdma1llclk 1.418 1.645 1.645 ps t control_ck cpmdma1llclk 0.555 0.717 0.717 ps t data_ck cpmdma1llclk 0.01 0.046 0.046 ps ta bl e 1 9 : processor block dma2 switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmdma2llclk 1.235 1.437 1.437 ps t ck_data cpmdma2llclk 1.262 1.463 1.463 ps t control_ck cpmdma2llclk 0.924 1.155 1.155 ps t data_ck cpmdma2llclk 0.142 0.168 0.168 ps ta bl e 2 0 : processor block dma3 switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmdma3llclk 1.242 1.462 1.462 ps t ck_data cpmdma3llclk 1.184 1.376 1.376 ps t control_ck cpmdma3llclk 0.767 0.965 0.965 ps t data_ck cpmdma3llclk 0.119 0.116 0.116 ps ta bl e 2 1 : processor block dcr switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmdcrclk ? ? ? t ck_address cpmdcrclk ? ? ? t ck_data cpmdcrclk ? ? ? t control_ck cpmdcrclk ? ? ? t address_ck cpmdcrclk ? ? ? t data_ck cpmdcrclk ? ? ?
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 11 ta bl e 2 2 : processor block fcm switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control cpmfcmclk 1.084 1.324 1.324 ps t ck_data cpmfcmclk 1.158 1.4 1.4 ps t ck_instruction cpmfcmclk 0.818 1.06 1.06 ps t control_ck cpmfcmclk 1.218 1.395 1.395 ps t data_ck cpmfcmclk 0.698 0.768 0.768 ps t result_ck cpmfcmclk 0.698 0.768 0.768 ps ta bl e 2 3 : processor block misc switching characteristics clock name reference clock speed grade units -2i -1i -1m clock-to-out and setup relative to clock t ck_control clk1 ? ? ? t ck_address clk2 ? ? ? t ck_data clk3 ? ? ? t control_ck clk4 ? ? ? t address_ck clk5 ? ? ? t data_ck clk6 ? ? ?
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 12 gtp_dual tile specifications gtp_dual tile dc characteristics ta bl e 2 4 : absolute maximum ratings for gtp_dual tiles symbol description units mgtavccpll analog supply voltage for the gtp_dual shared pll relative to gnd ?0.5 to 1.32 v mgtavtttx analog supply voltage for the gtp_dual transmitters relative to gnd ?0.5 to 1.32 v mgtavttrx analog supply voltage for the gtp_dual receivers relative to gnd ?0.5 to 1.32 v mgtavcc analog supply voltage for the gtp_dual common circuits relative to gnd ?0.5 to 1.1 v mgtavttrxc analog supply voltage for the resistor calibration circuit of the gtp_dual column ?0.5 to 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. ta bl e 2 5 : recommended operating conditions for gtp_dual tiles (1)(2) symbol description min max units mgtavccpll (1) analog supply voltage for the gtp_dual shared pll relative to gnd 1.14 1.26 v mgtavtttx (1) analog supply voltage for the gtp_dual transmitters relative to gnd 1.14 1.26 v mgtavttrx (1) analog supply voltage for the gtp_dual receivers relative to gnd 1.14 1.26 v mgtavcc (1) analog supply voltage for the gtp_dual common circuits relative to gnd 0.95 1.05 v mgtavttrxc (1) analog supply voltage for the resistor calibration circuit of the gtp_dual column 1.14 1.26 v notes: 1. each voltage listed requires the filter circuit described in virtex-5 fpga rocketio gtp transceiver user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. ta bl e 2 6 : dc characteristics over recommended operating conditions for gtp_dual tiles (1) symbol description min typ max units i mgtavtttx gtp_dual tile transmitter termination supply current (2) 71 90 ma i mgtavccpll gtp_dual tile shared pll supply current 36 60 ma i mgtavttrxc gtp_dual tile resistor termination calibration supply current 0.1 0.5 ma i mgtavttrx gtp_dual tile receiver termination supply current (3) 0.1 0.5 ma i mgtavcc gtp_dual tile internal analog supply current 56 110 ma mgtr ref precision reference resistor for internal calibration termination 49.9 1% tolerance ? notes: 1. typical values are specified at nominal voltage, 25c, with a 3.2 gb/s line rate. 2. i cc numbers are given per gtp_dual tile with both gtp transceivers operating with default settings. 3. ac coupled tx/rx link.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 13 gtp_dual tile dc input and output levels ta bl e 2 8 summarizes the dc output specifications of the gtp_dual tiles in virtex-5q fpgas. figure 1, page 14 shows the single-ended output voltage swing. figure 2, page 14 shows the peak-to-peak differential output voltage. consult virtex-5 fpga rocketio gtp transceiver user guide for further details. ta bl e 2 7 : gtp_dual tile quiescent supply current symbol description typ (1) max units i avtttxq quiescent mgtavtttx (transmitter te rmination) supply current 8.5 18 ma i avccpllq quiescent mgtavccpll (p ll) supply current 8 18 ma i avttrxq quiescent mgtavttrx (receiver termination) supply current. includes mgtavttrxcq. 0.1 0.8 ma i avccq quiescent mgtavcc (analog) supply current 2.5 11 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. device powered and unconfigured. 3. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 4. gtp_dual tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available gtp_dual tiles in the target lxt or sxt device. ta bl e 2 8 : gtp_dual tile dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled ? 3.2 gb/s 150 2000 mv external ac coupled ? 3.2 gb/s 180 2000 mv v in absolute input voltage dc coupled ?400 mgtavttrx + 400 up to 1320 mv v cmin common mode input voltage dc coupled mgtavttrx = 1.2v 800 mv dv ppout differential peak-to-peak output voltage (1) txbufdiffctrl = 000 , tx_diff_boost = on 1400 mv v seout single-ended output voltage swing (1) txbufdiffctrl = 000 , tx_diff_boost = on 700 mv v cmout common mode output voltage equation based mgtavtttx = 1.2v 1200 ? amplitude/2 mv r in differential input resistance 90 100 120 ? r out differential output resistance 90 100 120 ? t oskew transmitter output skew 15 ps c ext recommended external ac coupling capacitor (2) 75 100 200 nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in virtex-5 fpga rocke tio gtp transceiver user guide and can result in values lower than reported in this table. 2. values outside of this range can be used as appropriate to conform to specific protocols and standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 14 ta bl e 2 9 summarizes the dc specifications of the clock input of the gtp_dual tile. figure 3 shows the single-ended input voltage swing. figure 4 shows the peak-to-peak differential clock input voltage swing. consult virtex-5 fpga rocketio gtp transceiver user guide for further details. x-ref target - figure 1 figure 1: single-ended output voltage swing x-ref target - figure 2 figure 2: peak-to-peak differential output voltage ta bl e 2 9 : gtp_dual tile clock dc input specifications (1) symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage 200 800 2000 mv v ise single-ended input voltage 100 400 1000 mv r in differential input resistance 80 105 130 ? c ext required external ac coupling capacitor 75 100 200 nf notes: 1. v min = 0v and v max = 1200 mv x-ref target - figure 3 figure 3: single-ended clock input voltage swing peak-to-peak x-ref target - figure 4 figure 4: differential clock input voltage swing peak-to-peak 0 +v p n v s eout d s 714_01_012109 0 +v ?v p?n dv ppout dv ppin d s 714_02_012109 0 +v p n v i s e d s 714_0 3 _012109 0 +v ?v p ? n v idiff d s 714_04_012109
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 15 gtp_dual tile switching characteristics consult virtex-5 fpga rocketio gtp transceiver user guide for further information. ta bl e 3 0 : gtp_dual tile performance symbol description speed grade units -2i -1i f gtpmax maximum gtp transceiver data rate 3.75 3.2 gb/s f gpllmax maximum pll frequency 2.0 2.0 ghz f gpllmin minimum pll frequency 1.0 1.0 ghz ta bl e 3 1 : dynamic reconfiguration port (drp) in the gtp_dual tile switching characteristics symbol description speed grade units -2i -1i f gtpdrpclk gtpdrpclk maximum frequency 175 150 mhz ta bl e 3 2 : gtp_dual tile reference cloc k switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range (1) clk 60 350 mhz t rclk reference clock rise time 20% ? 80% 200 400 ps t fclk reference clock fall time 80% ? 20% 200 400 ps t dcref reference clock duty cycle (2) clk 405060% t gjtt reference clock total jitter, peak- peak (3) clk 40 ps t lock clock recovery frequency acquisition time initial pll lock 1 ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock 200 s notes: 1. the clock from the gtp_dual differential clock pin pair can be used for all serial bit rates. grefclk can be used for serial bi t rates up to 1 gb/s. 2. for reference clock rates above 325 mhz, a duty cycle of 45% to 55% must be maintained. 3. measured at the package pin. gtp_du al jitter characteristics measured using a clock with specification t gjtt . x-ref target - figure 5 figure 5: reference clock timing parameters d s 714_05_012109 8 0 % 20 % t fclk t rclk
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 16 ta bl e 3 3 : gtp_dual tile user clock switching characteristics (1) symbol description conditions speed grade units -2i -1i f txout txoutclk maximum frequency 375 320 mhz f rxrec rxrecclk maximum frequency 375 320 mhz t rx rxusrclk maximum frequency 375 320 mhz t rx2 rxusrclk2 maximum frequency rxdatawidth = 0 350 320 mhz rxdatawidth = 1 187.5 160 mhz t tx txusrclk maximum frequency 375 320 mhz t tx2 txusrclk2 maximum frequency txdatawidth = 0 350 320 mhz txdatawidth = 1 187.5 160 mhz notes: 1. clocking must be implemented as described in virtex-5 fpga rocketio gtp transceiver user guide. ta bl e 3 4 : gtp_dual tile transmitter switching characteristics symbol description min typ max units f gtptx serial data rate range 0.1 f gtpmax gb/s t rtx tx rise time 140 ps t ftx tx fall time 120 ps t llskew tx lane-to-lane skew (1) 855 ps v txoobvdpp electrical idle amplitude 20 mv t txoobtrans electrical idle transition time 40 ns t j3.75 total jitter (2) 3.75 gb/s 0.35 ui d j3.75 deterministic jitter (2) 0.19 ui t j3.2 total jitter (2) 3.20 gb/s 0.35 ui d j3.2 deterministic jitter (2) 0.19 ui t j2.5 total jitter (2) 2.50 gb/s 0.30 ui d j2.5 deterministic jitter (2) 0.14 ui t j2.0 total jitter (2) 2.00 gb/s 0.30 ui d j2.0 deterministic jitter (2) 0.14 ui t j1.25 total jitter (2) 1.25 gb/s 0.20 ui d j1.25 deterministic jitter (2) 0.10 ui t j1.00 total jitter (2) 1.00 gb/s 0.20 ui d j1.00 deterministic jitter (2) 0.10 ui t j500 total jitter (2) 500 mb/s 0.10 ui d j500 deterministic jitter (2) 0.04 ui t j100 total jitter (2) 100 mb/s 0.02 ui d j100 deterministic jitter (2) 0.01 ui notes: 1. using same refclk input with t xenpmaphasealign enabled for up to f our consecutive gtp_dual sites. 2. using pll_divsel_fb = 2, intdatawidth = 1. 3. all jitter values are based on a bit-error ratio of 1e ?12 .
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 17 ta bl e 3 5 : gtp_dual tile receiver switching characteristics symbol description min typ max units f gtprx serial data rate rx oversampler not enabled 0.5 f gtpmax gb/s rx oversampler enabled 0.1 0.5 gb/s r xoobvdpp oob detect threshold peak-to-peak oobdetect_threshold = 100 60 105 165 mv r xsst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 0 ppm r xrl run length (cid) internal ac capacitor bypassed 150 ui r xppmtol data/refclk ppm offset tolerance cdr 2 nd -order loop disabled with pll_rxdivsel_out = 1 (2) ?200 200 ppm cdr 2 nd -order loop disabled with pll_rxdivsel_out = 2 (2) ?200 200 ppm cdr 2 nd -order loop disabled with pll_rxdivsel_out = 4 (2) ?100 100 ppm cdr 2 nd -order loop enabled ?1000 1000 ppm sj jitter tolerance jt_sj 3.75 sinusoidal jitter (3) 3.75 gb/s 0.30 ui jt_sj 3.2 sinusoidal jitter (3) 3.20 gb/s 0.40 ui jt_sj 2.50 sinusoidal jitter (3) 2.50 gb/s 0.40 ui jt_sj 2.00 sinusoidal jitter (3) 2.00 gb/s 0.40 ui jt_sj 1.00 sinusoidal jitter (3) 1.00 gb/s 0.30 ui jt_sj 500 sinusoidal jitter (3) 500 mb/s 0.30 ui jt_sj 500 sinusoidal jitter (3) 500 mb/s os 0.30 ui jt_sj 100 sinusoidal jitter (3) 100 mb/s os 0.30 ui sj jitter tolerance with stressed eye jt_tjse 3.2 total jitter wi th stressed eye (4) 3.20 gb/s 0.87 ui jt_sjse 3.2 sinusoidal jitter with stressed eye (4) 3.20 gb/s 0.30 ui notes: 1. using pll_rxdivsel_out = 1 only. 2. cdr 1st-order step size set to 2. 3. using 80 mhz sinusoidal jitter only in the absence of deterministic and random jitter. 4. stimulus signal includes 0.4ui of dj and 0.17ui of rj. rx equalizer is enabled. 5. all jitter values are based on a bit error ratio of 1e ?12 .
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 18 gtx_dual tile specifications gtx_dual tile dc characteristics ta bl e 3 6 : absolute maximum ratings for gtx_dual tiles symbol description units mgtavccpll analog supply voltage for the gtx_dual shared pll relative to gnd ?0.5 to 1.1 v mgtavtttx analog supply voltage for the gtx_dual transmitters relative to gnd ?0.5 to 1.32 v mgtavttrx analog supply voltage for the gtx_dual receivers relative to gnd ?0.5 to 1.32 v mgtavcc analog supply voltage for the gtx_dual common circuits relative to gnd ?0.5 to 1.1 v mgtavttrxc analog supply voltage for the resistor calibration circuit of the gtx_dual column ?0.5 to 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. ta bl e 3 7 : recommended operating conditions for gtx_dual tiles (1)(2) symbol description min max units mgtavccpll (1) analog supply voltage for the gtx_dual shared pll relative to gnd 0.95 1.05 v mgtavtttx (1) analog supply voltage for the gtx_dual transmitters relative to gnd 1.14 1.26 v mgtavttrx (1) analog supply voltage for the gtx_dual receivers relative to gnd 1.14 1.26 v mgtavcc (1) analog supply voltage for the gtx_dual common circuits relative to gnd 0.95 1.05 v mgtavttrxc (1) analog supply voltage for the resistor calibration circuit of the gtx_dual column 1.14 1.26 v notes: 1. each voltage listed requires the filter circuit described in virtex-5 fpga rocketio gtx transceiver user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. ta bl e 3 8 : dc characteristics over recommended operating conditions for gtx_dual tiles (1) symbol description min typ max units i mgtavtttx gtx_dual tile transmitter termination supply current (2) 43.3 86.3 ma i mgtavccpll gtx_dual tile shared pll supply current 38.0 99.4 ma i mgtavttrxc gtx_dual tile resistor termination calibration supply current 0.1 0.5 ma i mgtavttrx gtx_dual tile receiver termination supply current (3) 40.3 56.5 ma i mgtavcc gtx_dual tile internal analog supply current 80.5 179.5 ma mgtr ref precision reference resistor for internal calibration termination 59.0 1% tolerance ? notes: 1. typical values are specified at nominal voltage, 25c, with a 3.2 gb/s line rate. 2. i cc numbers are given per gtx_dual tile with both gtx transceivers operating with default settings. 3. ac coupled tx/rx link. 4. values for currents other than the values specified in this table can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 19 gtx_dual tile dc input and output levels ta bl e 4 0 summarizes the dc output specifications of the gtx_dual tiles in virtex-5q fpgas. figure 6, page 20 shows the single-ended output voltage swing. figure 7, page 20 shows the peak-to-peak differential output voltage. consult virtex-5 fpga rocketio gtx transceiver user guide for further details. ta bl e 3 9 : gtx_dual tile quiescent supply current symbol description typ (1) max units i avtttxq quiescent mgtavtttx (transmitter te rmination) supply current 8.2 21.6 ma i avccpllq quiescent mgtavccpll (p ll) supply current 0.8 4.8 ma i avttrxq quiescent mgtavttrx (receiver termination) supply current. includes mgtavttrxcq. 1.2 12.0 ma i avccq quiescent mgtavcc (analog) supply current 9.0 50.4 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. device powered and unconfigured. 3. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpower analyzer (xpa) tools. 4. gtx_dual tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the nu mber of available gtx_dual tiles in the target fxt device. ta bl e 4 0 : gtx_dual tile dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled ? 4.25 gb/s 200 1800 mv external ac coupled ? 4.25 gb/s 125 1800 mv v in absolute input voltage dc coupled mgtavttrx = 1.2v ?400 mgtavttrx +400 up to 1320 mv v cmin common mode input voltage dc coupled mgtavttrx = 1.2v 800 mv dv ppout differential peak-to-peak output voltage (1) txbufdiffctrl = 111 1400 mv v seout single-ended output voltage swing (1) txbufdiffctrl = 111 700 mv v cmout common mode output voltage equation based mgtavtttx = 1.2v 1200?dv ppout /2 mv r in differential input resistance 85 100 120 ? r out differential output resistance 85 100 120 ? t oskew transmitter output skew 2 8 ps c ext recommended external ac coupling capacitor (2) 75 100 200 nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in virtex-5 fpga rocke tio gtx transceiver user guide and can result in values lower than reported in this table. 2. values outside of this range can be used as appropriate to conform to specific protocols and standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 20 ta bl e 4 1 summarizes the dc specifications of the clock input of the gtx_dual tile. figure 8 shows the single-ended input voltage swing. figure 9 shows the peak-to-peak differential clock input voltage swing. consult virtex-5 fpga rocketio gtx transceiver user guide for further details. x-ref target - figure 6 figure 6: single-ended output voltage swing x-ref target - figure 7 figure 7: peak-to-peak differential output voltage ta bl e 4 1 : gtx_dual tile clock dc input level specification (1) symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage 210 800 2000 mv v ise single-ended input voltage 105 400 750 mv r in differential input resistance 90 105 130 ? c ext required external ac coupling capacitor 100 nf notes: 1. v min = 0v and v max = 1200 mv x-ref target - figure 8 figure 8: single-ended clock input voltage swing peak-to-peak x-ref target - figure 9 figure 9: differential clock input voltage swing peak-to-peak 0 +v p n v s eout d s 714_06_012109 0 +v ?v p?n dv ppout dv ppin d s 714_07_012109 0 +v p n v i s e d s 714_0 8 _012109 0 +v ?v p ? n v idiff d s 714_09_012109
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 21 gtx_dual tile switching characteristics consult virtex-5 fpga rocketio gtx transceiver user guide for further information. ta bl e 4 2 : gtx_dual tile performance symbol description speed grade units -2i -1i -1m f gtxmax maximum gtx transceiver data rate 6.5 4.25 4.25 gb/s f gpllmax maximum pll frequency 3.25 3.25 3.25 ghz f gpllmin minimum pll frequency 1.5 1.5 1.5 ghz ta bl e 4 3 : dynamic reconfiguration port (drp) in the gtx_dual tile switching characteristics symbol description speed grade units -2i -1i -1m f gtxdrpclk gtxdrpclk maximum frequency 175 150 150 mhz ta bl e 4 4 : gtx_dual tile reference cloc k switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range (1) clk 60 650 mhz t rclk reference clock rise time 20% ? 80% 200 ps t fclk reference clock fall time 80% ? 20% 200 ps t dcref reference clock duty cycle clk 40 50 60 % t gjtt reference clock total jitter (2)(3) at 100 khz ?145 dbc/hz at 1 mhz ?150 dbc/hz t lock clock recovery frequency acquisition time initial pll lock 0.25 1 ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock 200 s notes: 1. grefclk can be used for serial bit rates up to 1 gb/s; however, jitter specifications are not guaranteed when using grefclk. 2. gtx_dual jitter characteristics measured using a clock with specification t gjtt . a reference clock with higher phase noise can be used with link margin trade off. 3. the selection of the reference clock is application dependent. this parameter describes the quality of the reference clock us ed during transceiver jitter characterization - see table 46, page 22 and table 47, page 23 . x-ref target - figure 10 figure 10: reference clock timing parameters d s 714_10_012109 8 0 % 20 % t fclk t rclk
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 22 ta bl e 4 5 : gtx_dual tile user clock switching characteristics symbol description conditions device speed grade units -2i -1i -1m f txout txoutclk maximum frequency internal 20-bit datapath fxt 325 212.5 212.5 mhz internal 16-bit datapath fxt 406.25 265.625 265.625 mhz f rxrec rxrecclk maximum frequency fxt 406.25 265.625 265.625 mhz t rx rxusrclk maximum frequency 2 byte or 4 byte interface fxt 406.25 265.625 265.625 mhz t rx2 rxusrclk2 maximum frequency 1 byte interface fxt 312.5 235.625 235.625 mhz 2 byte interface 390.625 265.625 265.625 mhz 4 byte interface 203.125 132.813 132.813 mhz t tx txusrclk maximum frequency 2 byte or 4 byte interface fxt 406.25 265.625 265.625 mhz t tx2 txusrclk2 maximum frequency 1 byte interface fxt 312.5 235.625 235.625 mhz 2 byte interface 390.625 265.625 265.625 mhz 4 byte interface 203.125 132.813 132.813 mhz ta bl e 4 6 : gtx_dual tile transmitter switching characteristics symbol description condi tion min typ max units f gtxtx serial data rate range 0.15 f gtxmax gb/s t rtx tx rise time 20%?80% 120 ps t ftx tx fall time 80%?20% 120 ps t llskew tx lane-to-lane skew (1) 350 ps v txoobvdpp electrical idle amplitude 15 mv t txoobtransition electrical idle transition time 75 ns t j6.5 total jitter (2) 6.5 gb/s 0.33 ui d j6.5 deterministic jitter (2) 0.17 ui t j5.0 total jitter (2) 5.0 gb/s 0.33 ui d j5.0 deterministic jitter (2) 0.15 ui t j4.25 total jitter (2) 4.25 gb/s 0.35 (5) ui d j4.25 deterministic jitter (2) 0.14 ui t j3.75 total jitter (2) 3.75 gb/s 0.34 ui d j3.75 deterministic jitter (2) 0.16 ui t j3.2 total jitter (2) 3.2 gb/s 0.20 ui d j3.2 deterministic jitter (2) 0.10 ui t j3.2l total jitter (2) 3.2 gb/s (3) 0.36 ui d j3.2l deterministic jitter (2) 0.16 ui t j2.5 total jitter (2) 2.5 gb/s 0.20 ui d j2.5 deterministic jitter (2) 0.08 ui t j1.25 total jitter (2) 1.25 gb/s 0.15 ui d j1.25 deterministic jitter (2) 0.06 ui t j750 total jitter (2)(4) 750 mb/s 0.10 ui d j750 deterministic jitter (2)(4) 0.03 ui t j150 total jitter (2)(4) 150 mb/s 0.02 ui d j150 deterministic jitter (2)(4) 0.01 ui notes: 1. using same refclk input with txenpmaphasealign enabled for up to four consecutive gtx_dual sites. 2. using pll_divsel_fb = 2, intdatawidth = 1. these values are not intended for protocol specific compliance determinations. 3. pll frequency at 1.6 ghz and outdiv = 1. 4. grefclk can be used for serial data rates up to 1.0 gb/s, but performance is not guaranteed. 5. m-temperature only (0.33 ui for i-temperature)
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 23 ta bl e 4 7 : gtx_dual tile receiver switching characteristics symbol description min typ max units f gtxrx serial data rate rx oversampler not enabled 0.75 f gtxmax gb/s rx oversampler enabled 0.15 0.75 gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data oobdetect_threshold = 110 75 ns r xoobvdpp oob detect threshold peak-to-peak oobdetect_threshold = 110 55 135 mv r xsst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 0 ppm r xrl run length (cid) internal ac capacitor bypassed 512 ui r xppmtol data/refclk ppm offset tolerance cdr 2 nd -order loop disabled ?200 200 ppm cdr 2 nd -order loop enabled ?2000 2000 ppm sj jitter tolerance (2) jt_sj 6.5 sinusoidal jitter (3) 6.5 gb/s 0.44 ui jt_sj 5.0 sinusoidal jitter (3) 5.0 gb/s 0.44 ui jt_sj 4.25 sinusoidal jitter (3) 4.25 gb/s 0.44 ui jt_sj 3.75 sinusoidal jitter (3) 3.75 gb/s 0.44 ui jt_sj 3.2 sinusoidal jitter (3) 3.2 gb/s 0.45 ui jt_sj 3.2l sinusoidal jitter (3) 3.2 gb/s (4) 0.45 ui jt_sj 2.5 sinusoidal jitter (3) 2.5 gb/s 0.50 ui jt_sj 1.25 sinusoidal jitter (3) 1.25 gb/s 0.50 ui jt_sj 750 sinusoidal jitter (3)(5) 750 mb/s 0.57 ui jt_sj 150 sinusoidal jitter (3)(5) 150 mb/s 0.57 ui sj jitter tolerance with stressed eye (2) jt_tjse 4.25 total jitter wi th stressed eye (6) 4.25 gb/s 0.69 ui jt_sjse 4.25 sinusoidal jitter with stressed eye (6) 4.25 gb/s 0.1 ui notes: 1. using pll_rxdivsel_out = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. using 80 mhz sinusoidal jitter only in the absence of deterministic and random jitter. 4. pll frequency at 1.6 ghz and outdiv = 1. 5. grefclk can be used for serial data rates up to 1.0 gb/s, but performance is not guaranteed. 6. composite jitter with rx equalizer enabled. dfe disabled.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 24 crc block switching characteristics ethernet mac switching characteristics consult virtex-5 fpga embedded tri-mode ethernet mac user guide for further information. endpoint block for pci express de signs switching characteristics consult virtex-5 fpga integrated endpoint block for pci express designs user guide for further information. ta bl e 4 8 : crc block switching characteristics symbol description speed grade units -2i -1i -1m f crc crcclk maximum frequency 325 270 270 mhz ta bl e 4 9 : maximum ethernet mac performance symbol description conditions speed grade units -2i -1i -1m f temacclient client interface maximum frequency 10 mb/s ? 8-bit width 1.25 1.25 1.25 mhz 100 mb/s ? 8-bit width 12.5 12.5 12.5 mhz 1000 mb/s ? 8-bit width 125 125 125 mhz 2000 mb/s ? 16-bit width 125 125 125 mhz f temacphy physical interface maximum frequency 10 mb/s ? 4-bit width 2.5 2.5 2.5 mhz 100 mb/s ? 4-bit width 25 25 25 mhz 1000 mb/s ? 8-bit width 125 125 125 mhz 2000 mb/s ? 8-bit width 250 250 250 mhz ta bl e 5 0 : maximum performance for pci express designs symbol description speed grade units -2i -1i -1m f pciecore core clock maximum frequency 250 250 250 mhz f pcieuser user clock maximum frequency 250 250 250 mhz
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 25 system monitor analog-to-digit al converter specification ta bl e 5 1 : analog-to-digital specifications parameter symbol comments/conditions min typ max units av dd =2.5v2%, v refp =2.5v, v refn = 0v, adcclk = 5.2 mhz, t a =t min to t max , typical values at t a =+25c dc accuracy: all external input channels such as v p /v n and v auxp [15:0]/v auxn [15:0], unipolar mode, and common mode = 0v resolution 10 bits integral nonlinearity inl 2 lsbs differential nonlinearity dnl no missing codes (t min to t max ) guaranteed monotonic 0.9 lsbs unipolar offset error (1) uncalibrated 2 30 lsbs bipolar offset error (1) uncalibrated measured in bipolar mode 2 30 lsbs gain error (1) uncalibrated, t j = ?40c to 100c 0.2 2.0 % uncalibrated, t j = ?55c to 125c 0.2 2.5 % bipolar gain error (1) uncalibrated measured in bipolar mode, t j = ?40c to 100c 0.2 2.0 % uncalibrated measured in bipolar mode, t j = ?55c to 125c 0.2 2.5 % total unadjusted error (uncalibrated) tue deviation from ideal transfer function. v refp ?v refn = 2.5v 10 lsbs total unadjusted error (calibrated) tue deviation from ideal transfer function. v refp ?v refn = 2.5v 1 2 lsbs calibrated gain temperature coefficient variation of fs code with temperature 0.01 lsb/ c dc common-mode reject cmrr dc v n = v cm = 0.5v 0.5v, v p ?v n = 100mv 70 db conversion rate (2) conversion time - continuous t conv number of clk cycles 26 32 conversion time - event t conv number of clk cycles 21 t/h acquisition time t acq number of clk cycles 4 drp clock frequency dclk drp clock frequency 8 250 mhz adc clock frequency adcclk derived from dclk, t j = ?40c to 100c 1 5.2 mhz derived from dclk, t j = ?55c to 125c 2.5 5.2 mhz clk duty cycle 40 60 % analog inputs (3) dedicated analog inputs input voltage range v p - v n unipolar operation 0 1 v differential inputs ?0.25 +0.25 unipolar common mode range (fs input) 0 +0.5 differential common mode range (fs input) +0.3 +0.7 bandwidth 20 mhz auxiliary analog inputs input voltage range v auxp[0] /v auxn[0] to v auxp[15] /v auxn[15] unipolar operation 0 1 volts differential operation ?0.25 +0.25 unipolar common mode range (fs input) 0 +0.5 differential common mode range (fs input) +0.3 +0.7 bandwidth 10 khz input leakage current a/d not converting, adcclk stopped 1.0 a input capacitance 10 pf on-chip supply monitor error v ccint and v ccaux with calibration enabled 1.0 % reading
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 26 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-5q devices. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the switching characteristics . ta b l e 5 2 shows internal (register-to-register) performance. on-chip temperature monitor error ?40c to +125c with calibration enabled 4 c external reference inputs (4) positive reference input voltage range v refp measured relative to v refn 2.45 2.5 2.55 volts negative reference input voltage range v refn measured relative to agnd ?50 0 100 mv input current i ref adcclk = 5.2 mhz 100 a power requirements analog power supply av dd measured relative to av ss 2.45 2.5 2.55 v analog supply current ai dd adcclk = 5.2 mhz 5 13 ma notes: 1. offset and gain errors are removed by enabling the system monitor automatic gain calibration feature. see virtex-5 fpga system monitor user guide . 2. see ?system monitor timing? in virtex-5 fpga system monitor user guide . 3. see ?analog inputs? in virtex-5 fpga system monitor user guide for a detailed description. 4. any variation in the reference voltage from the nominal v refp = 2.5v and v refn = 0v will result is a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing the supply voltage and reference to vary by 2% is permitted. ta bl e 5 2 : register-to-register performance description register-to-register (with i/o delays) units speed grade -2i -1i -1m basic functions 16:1 multiplexer 500 450 450 mhz 32:1 multiplexer 500 450 450 mhz 64:1 multiplexer 467 407 407 mhz 9 x 9 logic multiplier with 4 pipestages 438 428 428 mhz 9 x 9 logic multiplier with 5 pipestages 500 428 428 mhz 16-bit adder 500 450 450 mhz 32-bit adder 500 447 447 mhz 64-bit adder 377 323 323 mhz register to lut to register 500 450 450 mhz 16-bit counter 500 450 450 mhz 32-bit counter 500 450 450 mhz 64-bit counter 381 333 333 mhz memory cascaded block ram (64k) 450 400 400 mhz block ram pipelined single-port 512 x 36 bits 500 450 450 mhz single-port 4096 x 4 bits 500 450 450 mhz dual-port a: 4096 x 4 bits and b: 1024 x 18 bits 500 450 450 mhz ta bl e 5 1 : analog-to-digital specifications (cont?d) parameter symbol comments/conditions min typ max units
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 27 distributed ram single-port 16 x 8 500 450 450 mhz single-port 32 x 8 500 450 450 mhz single-port 64 x 8 500 450 450 mhz dual-port 16 x 8 mhz shift register chain 16-bit 500 450 450 mhz 32-bit 500 450 450 mhz 64-bit 500 438 438 mhz dedicated arithmetic logic dsp48e quad 12-bit adder/subtracter 500 450 450 mhz dsp48e dual 24-bit adder/subtracter 500 450 450 mhz dsp48e 48-bit adder/subtracter 500 450 450 mhz dsp48e 48-bit counter 500 450 450 mhz dsp48e 48-bit comparator 500 450 450 mhz dsp48e 25 x 18 bit pipelined multiplier 500 450 450 mhz dsp48e direct 4-tap fir filter pipelined 458 397 397 mhz dsp48e systolic n-tap fir filter pipelined 500 450 450 mhz notes: 1. device used is the xq5vlx50t- ff1136. ta bl e 5 3 : interface performances description speed grade -2i -1i -1m networking applications sfi-4.1 (sdr lvds interface) (1) 710 mhz 645 mhz 645 mhz spi-4.2 (ddr lvds interface) (2) 1.25 gb/s 1.0 gb/s 1.0 gb/s memory interfaces ddr (3) 200 mhz 200 mhz 200 mhz ddr2 (4) 300 mhz 267 mhz 267 mhz qdr ii sram (5) 300 mhz 250 mhz 250 mhz rldram ii (6) 300 mhz 250 mhz 250 mhz notes: 1. performance defined using design impl ementation described in application note xapp856 , sfi-4.1 16-channel sdr interface with bus alignment . 2. performance defined using design impl ementation described in application note xapp860 , 16-channel, ddr lvds interface with real-time window monitoring. 3. performance defined using design impl ementation described in application note xapp851 , ddr sdram controller. 4. performance defined using design impl ementation described in application note xapp858 , high-performance ddr2 sdram interface data capture. 5. performance defined using design impl ementation described in application note xapp853 , qdrii sram interface. 6. performance defined using design impl ementation described in application note xapp852 , synthesizable rldram ii controller . ta bl e 5 2 : register-to-register performance (cont?d) description register-to-register (with i/o delays) units speed grade -2i -1i -1m
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 28 switching characteristics all values represented in this data sheet are based on speed specification version 1.7 1. switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. all specifications are always representative of worst-case supply voltage and junction temperature conditions. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. ta b l e 5 4 correlates the current status of each virtex-5q device on a per speed grade basis. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-5q devices. ta b l e 5 4 : virtex-5q device speed grade designations device speed grade designations advance preliminary production xq5vlx30t -2i, -1i xq5vlx85 -2i, -1i xq5vlx110 -2i, -1i xq5vlx110t -2i, -1i xq5vlx155t -2i, -1i xq5vlx220t -2i, -1i xq5vlx330t -1i xq5vsx50t -2i, -1i xq5vsx95t -2i, -1i xq5vsx240t -1i xq5vfx70t -2i, -1i, -1m xq5vfx100t -2i, -1i, -1m xq5vfx130t -2i, -1i xq5vfx200t -1i
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 29 production silicon and ise software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta bl e 5 5 lists the production released virtex-5q family member, speed grade, and the minimum corresponding supported speed specification version and ise? software revisions. the ise software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. ta b l e 5 5 : virtex-5q device production software (1) and speed specification release device speed grade designations -2i -1i -1m xq5vlx30t ise 11.2 v1.65 n/a xq5vlx85 ise 11.2 v1.65 n/a xq5vlx110 ise 11.2 v1.65 n/a xq5vlx110t ise 11.2 v1.65 n/a xq5vlx155t ise 11.2 v1.65 n/a xq5vlx220t ise 12.2 v1.71 ise 11.2 v1.65 n/a xq5vlx330t n/a ise 11.2 v1.65 n/a xq5vsx50t ise 11.2 v1.65 n/a xq5vsx95t ise 12.2 v1.71 ise 11.2 v1.65 n/a xq5vsx240t n/a ise 11.2 v1.65 n/a xq5vfx70t ise 11.2 v1.65 ise 12.4 v1.71 xq5vfx100t ise 11.2 v1.65 ise 12.4 v1.71 xq5vfx130t ise 11.2 v1.65 n/a xq5vfx200t n/a ise 11.2 v1.65 n/a notes: 1. listed software revisions are those for production-released virtex-5q family members. 2. blank entries indicate a device and/or speed grade in advance or preliminary status.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 30 iob pad input/output/3-state switching characteristics ta bl e 5 6 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on th e capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of th e selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. table 57, page 34 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 5 6 : iob switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2(i) -1(i) -1(m) -2(i) -1(i) -1(m) -2(i) -1(i) -1(m) lvds_25 0.90 1.06 1.11 1.29 1.44 1.79 1.29 1.44 1.79 ns lvdsext_25 1.16 1.30 1.36 1.3 4 1.49 1.82 1.34 1.49 1.82 ns ht_25 0.90 1.06 1.11 1.26 1. 40 1.79 1.26 1.40 1.79 ns blvds_25 0.90 1.06 1.12 1.38 1.58 1.91 1.38 1.58 1.91 ns rsds_25 (point to point) 0.90 1.0 61.111.291.441.791.291.441.79 ns ulvds_25 0.90 1.06 1.11 1.27 1.41 1.79 1.27 1.41 1.79 ns pci33_3 0.70 0.82 1.05 2.06 2 .38 2.41 2.06 2.38 2.41 ns pci66_3 0.70 0.82 1.05 2.06 2 .38 2.41 2.06 2.38 2.41 ns pci-x 0.70 0.82 1.05 1.56 1 .80 2.03 1.56 1.80 2.03 ns gtl 0.85 1.00 1.11 1.63 1.8 62.101.631.862.10 ns gtlp 0.85 1.00 1.05 1.68 1. 93 2.14 1.68 1.93 2.14 ns hstl_i 0.85 1.00 1.07 1.57 1.79 1.96 1.57 1.79 1.96 ns hstl_ii 0.85 1.00 1.05 1.53 1 .74 1.84 1.53 1.74 1.84 ns hstl_iii 0.85 1.00 1.40 1.60 1.85 2.03 1.60 1.85 2.03 ns hstl_iv 0.85 1.00 1.40 1.60 1 .83 2.07 1.60 1.83 2.07 ns hstl_i _18 0.85 1.00 1.26 1. 55 1.77 1.91 1.55 1.77 1.91 ns hstl_ii _18 0.85 1.00 1.13 1.5 11.721.791.511.721.79 ns hstl_iii _18 0.85 1.00 1.45 1. 61 1.85 1.98 1.61 1.85 1.98 ns hstl_iv_18 0.85 1. 00 1.45 1.57 1.81 1. 92 1.57 1.81 1.92 ns sstl2_i 0.85 1.00 1.11 1.64 1.78 1.94 1.64 1.78 1.94 ns sstl2_ii 0.85 1.00 1.11 1.55 1 .76 1.83 1.55 1.76 1.83 ns lvttl, slow, 2 ma 0.70 0.82 1.0 24.475.016.054.475.016.05 ns lvttl, slow, 4 ma 0.70 0.82 1.0 23.093.414.133.093.414.13 ns lvttl, slow, 6 ma 0.70 0.82 1.0 22.913.293.912.913.293.91 ns lvttl, slow, 8 ma 0.70 0.82 1.0 22.302.612.912.302.612.91 ns lvttl, slow, 12 ma 0.70 0.82 1. 02 2.15 2.46 2.56 2.15 2.46 2.56 ns lvttl, slow, 16 ma 0.70 0.82 1. 02 2.04 2.34 2.47 2.04 2.34 2.47 ns lvttl, slow, 24 ma 0.70 0.82 1. 02 2.07 2.38 2.48 2.07 2.38 2.48 ns
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 31 lvttl, fast, 2 ma 0.70 0.82 1.0 23.614.055.583.614.055.58 ns lvttl, fast, 4 ma 0.70 0.82 1.0 22.552.903.722.552.903.72 ns lvttl, fast, 6 ma 0.70 0.82 1.0 22.312.633.342.312.633.34 ns lvttl, fast, 8 ma 0.70 0.82 1.0 21.822.092.391.822.092.39 ns lvttl, fast, 12 ma 0.70 0.82 1. 02 1.63 1.89 2.31 1.63 1.89 2.31 ns lvttl, fast, 16 ma 0.70 0.82 1. 02 1.57 1.81 2.27 1.57 1.81 2.27 ns lvttl, fast, 24 ma 0.70 0.82 1. 02 1.52 1.74 2.27 1.52 1.74 2.27 ns lvcmos33, slow, 2 ma 0.70 0.82 1.0 23.964.446.053.964.446.05 ns lvcmos33, slow, 4 ma 0.70 0.82 1.0 23.093.494.133.093.494.13 ns lvcmos33, slow, 6 ma 0.70 0.82 1.0 22.863.243.892.863.243.89 ns lvcmos33, slow, 8 ma 0.70 0.82 1.0 22.262.572.912.262.572.91 ns lvcmos33, slow, 12 ma 0.70 0.82 1. 02 2.14 2.42 2.56 2.14 2.42 2.56 ns lvcmos33, slow, 16 ma 0.70 0.82 1. 02 2.04 2.31 2.44 2.04 2.31 2.44 ns lvcmos33, slow, 24 ma 0.70 0.82 1. 02 2.07 2.35 2.48 2.07 2.35 2.48 ns lvcmos33, fast, 2 ma 0.70 0.82 1.0 23.203.595.563.203.595.56 ns lvcmos33, fast, 4 ma 0.70 0.82 1.0 22.502.843.702.502.843.70 ns lvcmos33, fast, 6 ma 0.70 0.82 1.0 22.272.593.322.272.593.32 ns lvcmos33, fast, 8 ma 0.70 0.82 1.0 21.792.052.351.792.052.35 ns lvcmos33, fast, 12 ma 0.70 0.82 1. 02 1.61 1.86 2.31 1.61 1.86 2.31 ns lvcmos33, fast, 16 ma 0.70 0.82 1. 02 1.56 1.80 2.28 1.56 1.80 2.28 ns lvcmos33, fast, 24 ma 0.70 0.82 1. 02 1.51 1.74 2.26 1.51 1.74 2.26 ns lvcmos25, slow, 2 ma 0.70 0.82 0.8 23.974.425.063.974.425.06 ns lvcmos25, slow, 4 ma 0.70 0.82 0.8 22.602.943.712.602.943.71 ns lvcmos25, slow, 6 ma 0.70 0.82 0.8 22.412.743.422.412.743.42 ns lvcmos25, slow, 8 ma 0.70 0.82 0.8 22.262.562.932.262.562.93 ns lvcmos25, slow, 12 ma 0.70 0.82 0. 82 2.31 2.63 2.73 2.31 2.63 2.73 ns lvcmos25, slow, 16 ma 0.70 0.82 0. 82 2.02 2.30 2.31 2.02 2.30 2.31 ns lvcmos25, slow, 24 ma 0.70 0.82 0. 82 2.04 2.34 2.37 2.04 2.34 2.37 ns lvcmos25, fast, 2 ma 0.70 0.82 0.8 23.413.824.483.413.824.48 ns lvcmos25, fast, 4 ma 0.70 0.82 0.8 22.082.373.232.082.373.23 ns lvcmos25, fast, 6 ma 0.70 0.82 0.8 21.922.202.891.922.202.89 ns lvcmos25, fast, 8 ma 0.70 0.82 0.8 21.832.092.381.832.092.38 ns lvcmos25, fast, 12 ma 0.70 0.82 0. 82 1.69 1.94 1.94 1.69 1.94 1.94 ns lvcmos25, fast, 16 ma 0.70 0.82 0. 82 1.60 1.85 1.99 1.60 1.85 1.99 ns lvcmos25, fast, 24 ma 0.70 0.82 0. 82 1.54 1.76 1.98 1.54 1.76 1.98 ns lvcmos18, slow, 2 ma 0.76 0.89 1.1 44.565.096.814.565.096.81 ns lvcmos18, slow, 4 ma 0.76 0.89 1.1 43.323.754.303.323.754.30 ns lvcmos18, slow, 6 ma 0.76 0.89 1.1 42.612.973.762.612.973.76 ns lvcmos18, slow, 8 ma 0.76 0.89 1.1 42.372.693.322.372.693.32 ns ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2(i) -1(i) -1(m) -2(i) -1(i) -1(m) -2(i) -1(i) -1(m)
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 32 lvcmos18, slow, 12 ma 0.76 0.89 1. 14 2.16 2.47 2.59 2.16 2.47 2.59 ns lvcmos18, slow, 16 ma 0.76 0.89 1. 14 2.14 2.45 2.53 2.14 2.45 2.53 ns lvcmos18, fast, 2 ma 0.76 0.89 1.1 43.714.166.233.714.166.23 ns lvcmos18, fast, 4 ma 0.76 0.89 1.1 42.612.983.802.612.983.80 ns lvcmos18, fast, 6 ma 0.76 0.89 1.1 42.062.353.302.062.353.30 ns lvcmos18, fast, 8 ma 0.76 0.89 1.1 41.872.132.661.872.132.66 ns lvcmos18, fast, 12 ma 0.76 0.89 1. 14 1.68 1.93 2.07 1.68 1.93 2.07 ns lvcmos18, fast, 16 ma 0.76 0.89 1. 14 1.61 1.86 1.97 1.61 1.86 1.97 ns lvcmos15, slow, 2 ma 0.83 0.98 1.2 33.844.345.083.844.345.08 ns lvcmos15, slow, 4 ma 0.83 0.98 1.2 32.402.743.482.402.743.48 ns lvcmos15, slow, 6 ma 0.83 0.98 1.2 32.202.522.552.202.522.55 ns lvcmos15, slow, 8 ma 0.83 0.98 1.2 32.122.432.462.122.432.46 ns lvcmos15, slow, 12 ma 0.83 0.98 1. 23 1.95 2.25 2.28 1.95 2.25 2.28 ns lvcmos15, slow, 16 ma 0.83 0.98 1. 23 1.91 2.20 2.23 1.91 2.20 2.23 ns lvcmos15, fast, 2 ma 0.83 0.98 1.2 33.073.484.993.073.484.99 ns lvcmos15, fast, 4 ma 0.83 0.98 1.2 31.952.233.391.952.233.39 ns lvcmos15, fast, 6 ma 0.83 0.98 1.2 31.802.062.411.802.062.41 ns lvcmos15, fast, 8 ma 0.83 0.98 1.2 31.742.002.261.742.002.26 ns lvcmos15, fast, 12 ma 0.83 0.98 1. 23 1.60 1.86 1.99 1.60 1.86 1.99 ns lvcmos15, fast, 16 ma 0.83 0.98 1. 23 1.53 1.77 1.92 1.53 1.77 1.92 ns lvcmos12, slow, 2 ma 0.96 1.14 1.6 13.984.585.583.984.585.58 ns lvcmos12, slow, 4 ma 0.96 1.14 1.6 12.332.663.132.332.663.13 ns lvcmos12, slow, 6 ma 0.96 1.14 1.6 12.182.452.542.182.452.54 ns lvcmos12, slow, 8 ma 0.96 1.14 1.6 12.142.482.512.142.482.51 ns lvcmos12, fast, 2 ma 0.96 1.14 1.6 13.383.875.543.383.875.54 ns lvcmos12, fast, 4 ma 0.96 1.14 1.6 11.912.203.011.912.203.01 ns lvcmos12, fast, 6 ma 0.96 1.14 1.6 11.782.082.441.782.082.44 ns lvcmos12, fast, 8 ma 0.96 1.14 1.6 11.701.972.281.701.972.28 ns lvdci_33 0.70 0.82 1.02 1.66 1.90 2.66 1.66 1.90 2.66 ns lvdci_25 0.70 0.82 0.82 1.71 1.93 2.65 1.71 1.93 2.65 ns lvdci_18 0.76 0.89 1.14 1.78 1.99 2.85 1.78 1.99 2.85 ns lvdci_15 0.83 0.98 1.23 1.75 2.02 2.74 1.75 2.02 2.74 ns lvdci_dv2_25 0.70 0.82 0.82 1.51 1.74 2.12 1.51 1.74 2.12 ns lvdci_dv2_18 0.76 0.89 1.14 1.60 1.85 2.16 1.60 1.85 2.16 ns lvdci_dv2_15 0.83 0.98 1.23 1.65 1.91 2.33 1.65 1.91 2.33 ns gtl_dci 0.85 1.00 1.11 1.47 1.65 1.79 1.47 1.65 1.79 ns gtlp_dci 0.85 1.00 1.05 1.52 1.76 1.94 1.52 1.76 1.94 ns lvpecl_25 0.90 1.06 1.12 1.42 1 .62 1.91 1.42 1.62 1.91 ns ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2(i) -1(i) -1(m) -2(i) -1(i) -1(m) -2(i) -1(i) -1(m)
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 33 hstl_i_12 0.85 1.00 1.08 1.61 1.85 1.98 1.61 1.85 1.98 ns hstl_i_dci 0.85 1.00 1.07 1. 56 1.77 1.98 1.56 1.77 1.98 ns hstl_ii_dci 0.85 1.00 1.05 1. 48 1.69 1.86 1.48 1.69 1.86 ns hstl_ii_t_dci 0.85 1.00 1.05 1. 56 1.77 1.98 1.56 1.77 1.98 ns hstl_iii_dci 0.85 1.00 1.40 1. 72 1.95 2.27 1.72 1.95 2.27 ns hstl_iv_dci 0.85 1.00 1.40 1. 46 1.64 1.84 1.46 1.64 1.84 ns hstl_i_dci_18 0.85 1.00 1.26 1 .50 1.70 1.95 1.50 1.70 1.95 ns hstl_ii_dci_18 0.85 1.00 1.13 1. 43 1.64 1.77 1.43 1.64 1.77 ns hstl_ii _t_dci_18 0.85 1.00 1.1 31.501.701.951.501.701.95 ns hstl_iii_dci_18 0.85 1.00 1.45 1 .69 1.91 2.16 1.69 1.91 2.16 ns hstl_iv_dci_18 0.85 1.00 1.45 1 .44 1.62 1.84 1.44 1.62 1.84 ns diff_hstl_i_18 0.90 1.06 1.10 1 .55 1.77 1.91 1.55 1.77 1.91 ns diff_hstl_i_dci_18 0.90 1.06 1.1 01.501.701.911.501.701.91 ns diff_hstl_i 0.90 1. 06 1.10 1.57 1.79 1. 91 1.57 1.79 1.91 ns diff_hstl_i_dci 0.90 1.06 1.10 1.56 1.77 1. 95 1.56 1.77 1.95 ns diff_hstl_ii_18 0.90 1.06 1.10 1.51 1.72 1. 91 1.51 1.72 1.91 ns diff_hstl_ii_dci_18 0.90 1.06 1.1 01.431.641.911.431.641.91 ns diff_hstl_ii 0.90 1.06 1.10 1.5 31.741.911.531.741.91 ns diff_hstl_ii_dci 0.90 1.06 1.10 1.48 1.69 1.91 1. 48 1.69 1.91 ns sstl2_i_dci 0.85 1.00 1.11 1. 56 1.78 3.30 1.56 1.78 3.30 ns sstl2_ii_dci 0.85 1.00 1.11 1. 48 1.70 1.97 1.48 1.70 1.97 ns sstl2_ii_t_dci 0.85 1.00 1.11 1. 56 1.78 3.30 1.56 1.78 3.30 ns sstl18_i 0.85 1.00 1.08 1.61 1 .84 1.94 1.61 1.84 1.94 ns sstl18_ii 0.85 1.00 1.08 1.53 1.75 1.81 1.53 1.75 1.81 ns sstl18_i_dci 0.85 1.00 1.08 1. 53 1.74 1.97 1.53 1.74 1.97 ns sstl18_ii_dci 0.85 1.00 1.08 1. 44 1.64 1.86 1.44 1.64 1.86 ns sstl18_ii_t_dci 0.85 1.00 1.08 1.53 1.74 1.97 1. 53 1.74 1.97 ns diff_sstl2_i 0.90 1. 06 1.11 1.64 1.87 1. 97 1.64 1.87 1.97 ns diff_sstl2_i_dci 0.90 1.06 1.11 1.56 1.78 1. 94 1.56 1.78 1.94 ns diff_sstl18_i 0.90 1.06 1.10 1.61 1.84 1.94 1.61 1.84 1.94 ns diff_sstl18_i_dci 0.90 1.06 1.10 1.53 1.74 1. 94 1.53 1.74 1.94 ns diff_sstl2_ii 0.90 1.06 1.11 1.5 5 1.76 1.91 1.55 1.76 1.91 ns diff_sstl2_ii_dci 0.90 1.06 1.11 1.48 1.70 1.90 1. 48 1.70 1.90 ns diff_sstl18_ii 0.90 1. 06 1.10 1.53 1.75 1. 91 1.53 1.75 1.91 ns diff_sstl18_ii_dci 0. 90 1.06 1.10 1.44 1.64 1.91 1.44 1.64 1.91 ns notes: 1. m-temperature iob delays are slightly larger than timing analyzer/speeds specification values. correct values are listed in t his table. it is necessary to allow for this difference in the design. ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2(i) -1(i) -1(m) -2(i) -1(i) -1(m) -2(i) -1(i) -1(m)
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 34 i/o standard adjustment measurement methodology input delay measurements ta bl e 5 8 shows the test setup parameters used for measuring input delay. ta bl e 5 7 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -2i -1i -1m t iotphz t input to pad high-impedance 1.01 1.12 1.12 ns ta bl e 5 8 : input delay measurement methodology description i/o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(5) v ref (1)(3)(5) lvttl (low-voltage transistor-transistor logic) lvttl 0 3.0 1.4 ? lvcmos (low-voltage cmos), 3.3v lvcmos33 0 3.3 1.65 ? lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? lvcmos, 1.2v lvcmos12 0 1.2 0.6 ? pci (peripheral component interconnect), 33 mhz, 3.3v pci33_3 per pci? specification ? pci, 66 mhz, 3.3v pci66_3 per pci specification ? pci-x, 133 mhz, 3.3v pcix per pci-x? specification ? gtl (gunning transceiver logic) gtl v ref ?0.2 v ref +0.2 v ref 0.80 gtl plus gtlp v ref ?0.2 v ref +0.2 v ref 1.0 hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class iii & iv hstl_iii, hstl_iv v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class iii & iv, 1.8v hstl_iii_18, hstl_iv_18 v ref ?0.5 v ref +0.5 v ref 1.08 sstl (stub terminated transceiver logic), class i & ii, 3.3v sstl3_i, sstl3_ii v ref ?1.00 v ref +1.00 v ref 1.5 sstl, class i & ii, 2. 5v sstl2_i, sstl2_ii v ref ?0.75 v ref +0.75 v ref 1.25 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 agp-2x/agp (accelerated graphics port) agp v ref ? (0.2 xv cco ) v ref + (0.2 xv cco ) v ref agp spec lvds (low-voltage differential signaling), 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (6) lvdsext (lvds extended mode), 2.5v lvdsext_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ldt (hypertransport), 2.5v ldt_25 0.6 ? 0.125 0.6 + 0.125 0 (6) lvpecl (low-voltage positive emitter-coupled logic), 2.5v lvpecl_25 1.15 ? 0.3 1.15 ? 0.3 0 (6) notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as for hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 11, page 35 . 6. the value given is the differential input voltage.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 35 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4" of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 11 and figure 12 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 5 9 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of step 2 and step 4 . the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 11 figure 11: single ended test setup v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 714_11_012109 x-ref target - figure 12 figure 12: differential test setup r ref v mea s + ? c ref fpga o u tp u t d s 714_12_012109 ta bl e 5 9 : output delay measurement methodology description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v) lvttl (low-voltage transistor-transistor logic) lvttl (all) 1m 0 1.4 0 lvcmos (low-voltage cmos), 3.3v lvcmos33 1m 0 1.65 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.6 0 pci (peripheral component interface), 33 mhz, 3.3v pci33_3 (rising edge) 25 10 (2) 0.94 0 pci33_3 (falling edge) 25 10 (2) 2.03 3.3 pci, 66 mhz, 3.3v pci66_3 (rising edge) 25 10 (2) 0.94 0 pci66_3 (falling edge) 25 10 (2) 2.03 3.3 pci-x, 133 mhz, 3.3v pcix (rising edge) 25 10 (3) 0.94 pcix (falling edge 25 10 (3) 2.03 3.3 gtl (gunning transceiver logic) gtl 25 0 0.8 1.2 gtl plus gtlp 25 0 1.0 1.5 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class iii hstl_iii 50 0 0.9 1.5
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 36 hstl, class iv hstl_iv 25 0 0.9 1.5 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hstl, class iii, 1.8v hstl_iii_18 50 0 1.1 1.8 hstl, class iv, 1.8v hstl_iv_18 25 0 1.1 1.8 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl, class i, 2.5v sstl2_i 50 0 v ref 1.25 sstl, class ii, 2.5v sstl2_ii 25 0 v ref 1.25 lvds (low-voltage differential signaling), 2.5v lvds_25 100 0 0 (4) 1.2 lvdsext (lvds extended mode), 2.5v lvds_25 100 0 0 (4) 1.2 blvds (bus lvds), 2.5v blvds_25 100 0 0 (4) 0 ldt (hypertransport), 2.5v ldt_25 100 0 0 (4) 0.6 lvpecl (low-voltage positi ve emitter-coupled logic), 2.5v lvpecl_25 100 0 0 (4) 0 lvdci/hslvdci (low-voltage digitally controlled impedance), 3.3v lvdci_33, hslvdci_33 1m 0 1.65 0 lvdci/hslvdci, 2.5v lvdci_25, hslvdci_25 1m 0 1.25 0 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 1m 0 0.9 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 1m 0 0.75 0 hstl (high-speed transceiver logic), class i & ii, with dci hstl_i_dci, hstl_ii_dci 50 0 v ref 0.75 hstl, class iii & iv, with dci hstl_iii_dci, hstl_iv_dci 50 0 0.9 1.5 hstl, class i & ii, 1.8v, with dci hstl_i_dci_18, hstl_ii_dci_18 50 0 v ref 0.9 hstl, class iii & iv, 1.8v, with dci hstl_iii_dci_18, hstl_iv_dci_18 50 0 1.1 1.8 sstl (stub series termi.logic), class i & ii, 1.8v, with dci sstl18_i_dci, sstl18_ii_dci 50 0 v ref 0.9 sstl, class i & ii, 2.5v, with dci sstl2_i_dci, sstl2_ii_dci 50 0 v ref 1.25 gtl (gunning transceiver logic) with dci gtl_dci 50 0 0.8 1.2 gtl plus with dci gtlp_dci 50 0 1.0 1.5 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. per pci specifications. 3. per pci-x specifications. 4. the value given is the differential input voltage. ta bl e 5 9 : output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v)
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 37 input/output logic switching characteristics ta bl e 6 0 : ilogic switching characteristics symbol description speed grade units -2i -1i -1m setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to clk 0.49 ?0.24 0.59 ?0.24 0.59 ?0.17 ns t isrck /t icksr sr/rev pin setup/hold with respect to clk 1.00 ?0.20 1.22 ?0.20 1.22 ?0.22 ns t idock /t iockd d pin setup/hold with respect to clk without delay 0.37 ?0.12 0.39 ?0.12 0.39 ?0.12 ns t idockd /t iockdd ddly pin setup/hold with res pect to clk (using iodelay) 0.33 ?0.09 0.36 ?0.08 0.36 ?0.08 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.26 0.30 0.30 ns t idid ddly pin to o pin propagation delay (using iodelay) 0.22 0.26 0.26 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.50 0.58 0.58 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using iodelay) 0.46 0.55 0.55 ns t ickq clk to q outputs 0.52 0.60 0.60 ns t rq sr/rev pin to oq/tq out 1.28 1.53 1.53 ns t gsrq global set/reset to q outputs 7.30 10.10 10.10 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.95 1.20 1.20 ns, min ta bl e 6 1 : ologic switching characteristics symbol description speed grade units -2i -1i -1m setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0.36 ?0.21 0.44 ?0.21 0.44 ?0.14 ns t ooceck /t ockoce oce pin setup/hold with respect to clk 0.19 ?0.07 0.23 ?0.07 0.23 ?0.04 ns t osrck /t ocksr sr/rev pin setup/hold with respect to clk 1.02 ?0.20 1.16 ?0.20 1.16 ?0.20 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk 0.34 ?0.18 0.41 ?0.18 0.41 ?0.12 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.23 ?0.06 0.29 ?0.06 0.29 ?0.01 ns combinatorial t doq d1 to oq out or t1 to tq out 0.70 0.83 0.83 ns sequential delays t ockq clk to oq/tq out 0.62 0.62 0.62 ns t rq sr/rev pin to oq/tq out 1.89 2.27 2.27 ns t gsrq global set/reset to q outputs 7.30 10.10 10.10 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.98 1.25 1.25 ns, min
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 38 input serializer/deserializer switching characteristics ta bl e 6 2 : iserdes switching characteristics symbol description speed grade units -2i -1i -1m setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.11 0.00 0.12 0.00 0.12 0.00 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.49 ?0.24 0.59 ?0.24 0.59 ?0.17 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) 0.04 0.13 0.06 0.15 0.06 0.15 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk 0.37 ?0.12 0.39 ?0.12 0.39 ?0.12 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using iodelay) 0.33 ?0.09 0.36 ?0.08 0.36 ?0.08 ns t isdck_ddr /t isckd_ddr d pin setup/hold with respect to clk at ddr mode 0.37 ?0.12 0.39 ?0.12 0.39 ?0.12 ns t isdck_ddly_ddr t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using iodelay) 0.33 ?0.09 0.36 ?0.08 0.36 ?0.08 ns sequential delays t iscko_q clkdiv to out at q pin 0.51 0.60 0.60 ns propagation delays t isdo_do d input to do output pin 0.22 0.26 0.26 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in trace report.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 39 output serializer/deserializ er switching characteristics ta bl e 6 3 : oserdes switching characteristics symbol description speed grade units -2i -1i -1m setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkdiv 0.24 ?0.02 0.30 ?0.02 0.30 ?0.02 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0.34 ?0.18 0.41 ?0.18 0.41 ?0.12 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.24 ?0.03 0.28 ?0.03 0.28 ?0.03 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.19 ?0.07 0.23 ?0.07 0.23 ?0.04 ns t oscck_s sr (reset) input setup with re spect to clkdiv 0.58 0.70 0.70 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.23 ?0.06 0.29 ?0.06 0.29 ?0.01 ns sequential delays t oscko_oq clock to out from clk to oq 0.60 0.61 0.61 ns t oscko_tq clock to out from clk to tq 0.62 0.62 0.62 ns combinatorial t osdo_ttq t input to tq out 0.70 0.83 0.83 ns t osco_oq asynchronous reset to oq 1.82 2.19 2.19 ns t osco_tq asynchronous reset to tq 1.89 2.27 2.27 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t/ t osckd_t in trace report.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 40 input/output delay swit ching characteristics clb switching characteristics ta bl e 6 4 : input/output delay switching characteristics symbol description speed grade units -2i -1i -1m idelayctrl t idelayctrlco_rdy reset to ready for idelayctrl 3.00 3.00 3.00 s f idelayctrl_ref refclk frequency 200.00 200.00 200.00 mhz idelayctrl_ref_precision refclk precision 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 50.00 50.00 50.00 ns iodelay t idelayresolution iodelay chain delay resolution 1/(64 x f ref x1e 6 ) (1) ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern 000note2 pattern dependent period jitter in delay chain for random data pattern (prbs 23) 5 5 5 note 2 t iodelay_clk_max maximum frequency of clk input to iodelay 250 250 250 mhz t iodcck_ce / t iodckc_ce ce pin setup/hold with respect to ck 0.34 ?0.06 0.42 ?0.06 0.42 ?0.06 ns t iodck_inc / t iodckc_inc inc pin setup/hold with respect to ck 0.20 0.04 0.24 0.06 0.24 0.06 ns t iodck_rst / t iodckc_rst rst pin setup/hold with respect to ck 0.28 ?0.12 0.33 ?0.12 0.33 ?0.12 ns t ioddo_t tscontrol delay to muxe/muxf switching and through iodelay note 3 note 3 note 3 t ioddo_idatain propagation delay through iodelay note 3 note 3 note 3 t ioddo_odatain propagation delay through iodelay note 3 note 3 note 3 notes: 1. average tap delay at 200 mhz = 78 ps. 2. units in ps, peak-to-peak per tap, in high performance mode. 3. delay depends on iodelay tap setting. see trace report for actual values. ta bl e 6 5 : clb switching characteristics symbol description speed grade units -2i -1i -1m combinatorial delays t ilo an ? dn lut address to a 0.09 0.10 0.10 ns, max an ? dn lut address to amux/cmux 0.22 0.25 0.25 ns, max an ? dn lut address to bmux_a 0.35 0.40 0.40 ns, max t ito an ? dn inputs to a ? d q outputs 0.77 0.90 0.90 ns, max t axa ax inputs to amux output 0.44 0.53 0.53 ns, max t axb ax inputs to bmux output 0.52 0.61 0.61 ns, max t axc ax inputs to cmux output 0.36 0.42 0.42 ns, max t axd ax inputs to dmux output 0.62 0.73 0.73 ns, max t bxb bx inputs to bmux output 0.41 0.48 0.48 ns, max
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 41 t bxd bx inputs to dmux output 0.51 0.59 0.59 ns, max t cxb cx inputs to cmux output 0.36 0.42 0.42 ns, max t cxd cx inputs to dmux output 0.42 0.49 0.49 ns, max t dxd dx inputs to dmux output 0.42 0.49 0.49 ns, max t opcya an input to cout out put 0.50 0.59 0.59 ns, max t opcyb bn input to cout out put 0.44 0.51 0.51 ns, max t opcyc cn input to cout output 0.37 0.43 0.43 ns, max t opcyd dn input to cout output 0.34 0.40 0.40 ns, max t axcy ax input to cout output 0.42 0.50 0.50 ns, max t bxcy bx input to cout output 0.30 0.37 0.37 ns, max t cxcy cx input to cout outp ut 0.22 0.26 0.26 ns, max t dxcy dx input to cout outp ut 0.22 0.26 0.26 ns, max t byp cin input to cout output 0.10 0.11 0.11 ns, max t cina cin input to amux output 0.27 0.31 0.31 ns, max t cinb cin input to bmux output 0.30 0.35 0.35 ns, max t cinc cin input to cmux output 0.32 0.36 0.36 ns, max t cind cin input to dmux output 0.35 0.41 0.41 ns, max sequential delays t cko clock to aq ? dq outputs 0.40 0.47 0.47 ns, max setup and hold times of clb flip-flops before/after clock clk t dick /t ckdi ax ? dx input to clk on a ? d flip flops 0.41 0.21 0.49 0.24 0.49 0.31 ns, min t rck dx input to clk when used as rev 0.42 0.51 0.51 ns, min t ceck /t ckce ce input to clk on a ? d flip flops 0.20 ?0.04 0.23 ?0.04 0.23 ?0.03 ns, min t srck /t cksr sr input to clk on a ? d flip flops 0.49 ?0.19 0.59 ?0.19 0.59 ?0.19 ns, min t cinck /t ckcin cin input to clk on a ? d flip flops 0.16 0.16 0.18 0.19 0.18 0.26 ns, min set/reset t srmin sr input minimum pulse width 0.90 0.90 0.90 ns, min t rq delay from sr or rev input to aq ? dq flip-flops 0.86 1.03 1.03 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.52 0.63 0.63 ns, max f tog toggle frequency (for export control) 1265 1098 1098 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ?best-case ?, but if a ?0? is listed, there is no positive hold time. 2. these items are of interest for carry chain applications. ta bl e 6 5 : clb switching characteristics (cont?d) symbol description speed grade units -2i -1i -1m
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 42 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) ta bl e 6 6 : clb distributed ram swit ching characteristics symbol description speed grade units -2i -1i -1m sequential delays t shcko clock to a ? b outputs 1.26 1.54 1.54 ns, max t shcko_1 clock to amux ? bmux outputs 1.38 1.68 1.68 ns, max setup and hold times before/after clock clk t ds /t dh a ? d inputs to clk 0.84 0.22 1.03 0.26 1.03 0.26 ns, min t as /t ah address an inputs to clock 0.46 0.22 0.54 0.27 0.54 0.27 ns, min t ws /t wh we input to clock 0.39 ?0.04 0.46 ?0.02 0.46 ?0.02 ns, min t ceck /t ckce ce input to clk 0.42 ?0.07 0.51 ?0.06 0.51 ?0.06 ns, min clock clk t mpw minimum pulse width 0.82 1.00 1.00 ns, min t mcp minimum clock period 1.64 2.00 2.00 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. 2. t shcko also represents the clk to xmux output. refer to trace report for the clk to xmux path. ta bl e 6 7 : clb shift register switching characteristics symbol description speed grade units -2i -1i -1m sequential delays t reg clock to a ? d outputs 1.43 1.73 1.73 ns, max t reg_mux clock to amux ? dmux output 1.55 1.87 1.87 ns, max t reg_m31 clock to dmux output via m31 output 1.15 1.38 1.38 ns, max setup and hold times before/after clock clk t ws /t wh we input 0.24 ?0.04 0.29 ?0.02 0.29 ?0.02 ns, min t ceck /t ckce ce input to clk 0.27 ?0.07 0.33 ?0.06 0.33 ?0.06 ns, min t ds /t dh a ? d inputs to clk 0.66 0.09 0.78 0.11 0.78 0.11 ns, min clock clk t mpw minimum pulse width 0.70 0.85 0.85 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 43 block ram and fifo switching characteristics ta bl e 6 8 : block ram and fifo switching characteristics symbol description speed grade units -2i -1i -1m block ram and fifo clock to out delays t rcko_do and t rcko_dor (1) clock clk to dout output (without output register) (2)(3) 1.92 2.19 2.19 ns, max clock clk to dout output (with output register) (4)(5) 0.69 0.82 0.82 ns, max clock clk to dout output with ecc (without output register) (2)(3) 3.03 3.61 3.61 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.77 0.93 0.93 ns, max clock clk to dout output wi th cascade (without output register) (2) 2.44 2.94 2.94 ns, max clock clk to dout output with cascade (with output register) (4) 1.07 1.30 1.30 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.87 1.02 1.02 ns, max t rcko_pointers clock clk to fifo pointer outputs (7) 1.26 1.48 1.48 ns, max t rcko_eccr clock clk to biterr (with output register) 0.77 0.93 0.93 ns, max t rcko_ecc clock clk to biterr (without output register) 2.85 3.41 3.41 ns, max clock clk to eccparity in stan dard ecc mode 1.47 1.74 1.74 ns, max clock clk to eccparity in ecc enc ode only mode 0.89 1.05 1.05 ns, max setup and hold times before/after clock clk t rcck_addr /t rckc_addr addr inputs (8) 0.40 0.32 0.48 0.36 0.48 0.36 ns, min t rdck_di /t rckd_di din inputs (9) 0.30 0.28 0.35 0.29 0.35 0.29 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with ecc in standard mode (9) 0.37 0.33 0.42 0.36 0.42 0.47 ns, min din inputs with ecc encode only (9) 0.72 0.33 0.77 0.36 0.77 0.47 ns, min t rcck_en /t rckc_en block ram enable (en) input 0.36 0.15 0.42 0.15 0.42 0.15 ns, min t rcck_regce /t rckc_regce ce input of output register 0.16 0.24 0.18 0.27 0.18 0.27 ns, min t rcck_ssr /t rckc_ssr synchronous set/ reset (ssr) input 0.21 0.25 0.26 0.28 0.26 0.28 ns, min t rcck_we /t rckc_we write enable (we) input 0.51 0.17 0.63 0.18 0.63 0.18 ns, min t rcck_wren /t rckc_wren wren/rden fifo inputs (10) 0.41 0.34 0.48 0.40 0.48 0.40 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (11) 1.26 1.48 1.48 ns, max
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 44 dsp48e switching characteristics maximum frequency f max block ram in all modes 500 450 450 mhz f max_cascade block ram in cascade configuration 450 400 400 mhz f max_fifo fifo in all modes 500 450 450 mhz f max_ecc block ram and fifo in ecc configuration 375 325 325 mhz notes: 1. trace will report all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (a synchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr . 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount . 8. the addr setup and hold must be met when en is asserted even though we is deasserted. otherwise, block ram data corruption is possible. 9. t rcko_di includes both a and b inputs as we ll as the parity inputs of a and b. 10. these parameters also apply to rden. 11. t rco_flags includes the following flags: aempty, afull, empty, full, rderr, wrerr, rdcount, and wrcount. ta bl e 6 9 : dsp48e switching characteristics symbol description speed grade units -2i -1i -1m setup and hold times of data/control pins to the input register clock tdspdck_{aa, bb, acina, bcinb}/ tdspckd_{aa, bb, acina, bcinb} {a, b, acin, bcin} input to {a, b} register clk 0.21 0.23 0.26 0.30 0.26 0.30 ns tdspdck_cc/tdspckd_cc c input to c register clk 0.16 0.31 0.20 0.37 0.20 0.50 ns setup and hold times of data pins to the pipeline register clock tdspdck_{am, bm, acinm, bcinm}/ tdspckd_{am, bm, acinm, bcinm} {a, b, acin, bcin} input to m register clk 1.44 0.19 1.71 0.19 1.71 0.19 ns setup and hold times of data/control pins to the output register clock tdspdck_{ap, bp, acinp, bcinp}_m/ tdspckd_{ap, bp, acinp, bcinp}_m {a, b, acin, bcin} input to p register clk using multiplier 2.74 ?0.30 3.25 ?0.30 3.25 ?0.30 ns tdspdck_{ap, bp, acinp, bcinp}_nm/ tdspckd_{ap, bp, acinp, bcinp}_nm {a, b, acin, bcin} input to p register clk not using multiplier 1.54 ?0.10 1.83 ?0.10 1.83 ?0.10 ns tdspdck_cp/tdspckd_cp c in put to p register clk 1.42 ?0.13 1.70 ?0.13 1.70 ?0.13 ns tdspdck_{pcinp, crycinp, multsigninp}/ tdspckd_{pcinp, crycinp, multsigninp} {pcin, carrycascin, multsignin} input to p register clk 1.17 0.11 1.31 0.11 1.31 0.11 ns setup and hold times of the ce pins tdspcck_{cea1a, cea2a, ceb1b, ceb2b}/ tdspckc_{cea1a, cea2a, ceb1a, ceb2b} {cea1, cea2a, ceb1b, ceb2b} input to {a, b} register clk 0.28 0.25 0.33 0.31 0.33 0.31 ns tdspcck_cecc/tdspckc_cecc cec input to c register clk 0.21 0.21 0.26 0.28 0.26 0.28 ns tdspcck_cemm/tdspckc_cemm cem input to m register clk 0.29 0.21 0.36 0.26 0.36 0.26 ns ta bl e 6 8 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -2i -1i -1m
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 45 tdspcck_cepp/tdspckc_cepp cep input to p register clk 0.63 0.01 0.73 0.01 0.73 0.01 ns setup and hold times of the rst pins tdspcck_{rstaa, rstbb}/ tdspckc_{rstaa, rstbb} {rsta, rstb} input to {a, b} register clk 0.28 0.26 0.33 0.31 0.33 0.31 ns tdspcck_rstcc/ tdspckc_rstcc rstc input to c register clk 0.21 0.21 0.26 0.28 0.26 0.28 ns tdspcck_rstmm/ tdspckc_rstmm rs tm input to m register clk 0.29 0.21 0.36 0.26 0.36 0.26 ns tdspcck_rstpp/tdspckc_rstpp rstp input to p register clk 0.63 0.01 0.73 0.01 0.73 0.01 ns combinatorial delays from input pins to output pins tdspdo_{ap, acryout, bp, bcryout}_m {a, b} input to {p, carryout} output using multiplier 3.22 3.84 3.84 ns tdspdo_{ap, acryout, bp, bcryout}_nm {a, b} input to {p, carryout} output not using multiplier 1.77 2.22 2.22 ns tdspdo_{cp, ccryout, cryinp, cryincryout} {c, carryin} input to {p, carryout} output 1.67 2.08 2.08 ns combinatorial delays from input pins to cascading output pins tdspdo_{aacout, bbcout} {a, b} input to {acout, bcout} output 1.12 1.31 1.31 ns tdspdo_{apcout, acrycout, amultsignout, bpcout, bcrycout, bmultsignout}_m {a, b} input to {pcout, carrycascout, multsignout} output using multiplier 3.22 3.84 3.84 ns tdspdo_{apcout, acrycout, amultsignout, bpcout, bcrycout, bmultsignout}_nm {a, b} input to {pcout, carrycascout, multsignout} output not using multiplier 1.92 2.42 2.42 ns tdspdo_{cpcout, ccrycout, cmultsignout, cryinpcout, cryincrycout, cryinmultsignout} {c, carryin} input to {pcout, carrycascout, multsignout} output 1.82 2.28 2.28 ns combinatorial delays from cascading input pins to all output pins tdspdo_{acinp, acincryout, bcinp, bcincryout}_m {acin, bcin} input to {p, carryout} output using multiplier 3.22 3.84 3.84 ns tdspdo_{acinp, acincryout, bcinp, bcincryout}_nm {acin, bcin} input to {p, carryout} output not using multiplier 1.77 2.22 2.22 ns tdspdo_{acinacout, bcinbcout} {acin, bcin} input to {acout, bcout} output 1.12 1.31 1.31 ns tdspdo_{acinpcout, acincrycout, acinmultsignout, bcinpcout, bcincrycout, bcinmultsignout}_m {acin, bcin} input to {pcout, carrycascout, multsignout} output using multiplier 3.22 3.84 3.84 ns tdspdo_{acinpcout, acincrycout, acinmultsignout, bcinpcout, bcincrycout, bcinmultsignout}_nm {acin, bcin} input to {pcout, carrycascout, multsignout} output not using multiplier 1.92 2.42 2.42 ns tdspdo_{pcinp, crycinp, multsigninp, pcincryout, crycincryout, multsignincryout} {pcin, carrycascin, multsignin} input to {p, carryout} output 1.45 1.82 1.82 ns ta bl e 6 9 : dsp48e switching characteristics (cont?d) symbol description speed grade units -2i -1i -1m
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 46 tdspdo_{pcinpcout, crycinpcout, multsigninpcout, pcincrycout, crycincrycout, multsignincrycout, pcinmultsignout, crycinmultsignout, multsigninmultsignout} {pcin, carrycascin, multsignin} input to {pcout, carrycascout, multsignout} output 1.60 2.02 2.02 ns clock to outs from output re gister clock to output pins tdspcko_{pp, cryoutp} clk (preg) to {p, carryout} output 0.48 0.56 0.56 ns tdspcko_{crycoutp, pcoutp, multsignoutp} clk (preg) to {carrycascout, pcout, multsignout} output 0.53 0.62 0.62 ns clock to outs from pipeline register clock to output pins tdspcko_{pm, cryoutm} clk (mreg) to {p, carryout} output 2.10 2.47 2.47 ns tdspcko_{pcoutm, crycoutm, multsignoutm} clk (mreg) to {pcout, carrycascout, multsignout} output 2.13 2.66 2.66 ns clock to outs from input re gister clock to output pins tdspcko_{pa, cryouta, pb, cryoutb}_m clk (areg, breg) to {p, carryout} output using multiplier 3.57 4.23 4.23 ns tdspcko_{pa, cryouta, pb, cryoutb}_nm clk (areg, breg) to {p, carryout} output not using multiplier 2.11 2.63 2.63 ns tdspcko_{pc, cryoutc} clk (creg) to {p, carryout} output 2.11 2.62 2.62 ns clock to outs from input regist er clock to cascading output pins tdspcko_{acouta, bcoutb} clk (areg, breg) to {acout, bcout} 0.68 0.79 0.79 ns tdspcko_{pcouta, crycouta, multsignouta, pcoutb, crycoutb, multsignoutb}_m clk (areg, breg) to {pcout, carrycascout, multsignout} output using multiplier 3.57 4.23 4.23 ns tdspcko_{pcouta, crycouta, multsignouta, pcoutb, crycoutb, multsignoutb}_nm clk (areg, breg) to {pcout, carrycascout, multsignout} output not using multiplier 2.27 2.82 2.82 ns tdspcko_{pcoutc, crycoutc, multsignoutc} clk (creg) to {pcout, carrycascout, multsignout} output 2.26 2.82 2.82 ns maximum frequency f max with all registers used 500 450 450 mhz f max_patdet with pattern detector 465 410 410 mhz f max_mult_nomreg two register multiply without mreg 324 275 275 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 300 254 254 mhz ta bl e 6 9 : dsp48e switching characteristics (cont?d) symbol description speed grade units -2i -1i -1m
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 47 configuration switching characteristics ta bl e 7 0 : configuration switching characteristics symbol description speed grade units -2i -1i -1m power-up timing characteristics t pl program latency 3 3 3 ms, max t por power-on-reset 10 50 10 50 10 50 ms, min/max t icck cclk (output) delay 400 400 400 ns, min t program program pulse width 250 250 250 ns, min master/slave serial mode programming switching (1) t dcck /t cckd din setup/hold, slave mode 4.0 0.0 4.0 0.0 5.0 0.0 ns, min t dscck /t scckd din setup/hold, master mode 4.0 0.0 4.0 0.0 5.0 0.0 ns, min t cco dout 7.5 7.5 7.5 ns, max f mcck maximum frequency, master mode with respect to nominal cclk. 100 100 100 mhz, max f mccktol frequency tolerance, master mode with respect to nominal cclk. 50 50 50 % f mscck slave mode external cclk 100 100 100 mhz selectmap mode programming switching (1) t smdcck /t smcckd selectmap data setup/hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, min t smcscck /t smcckcs cs_b setup/hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, min t smcckw /t smwcck rdwr_b setup/hold 8.0 0.5 8.0 0.5 8.0 0.5 ns, min t smckcso cso_b clock to out (330 ? pull-up resistor required) 10 10 10 ns, min t smco cclk to data out in readback 9.0 9.0 9.0 ns, max t smckby cclk to busy out in readback 7.5 7.5 7.5 ns, max f smcck maximum frequency with respect to nominal cclk 100 100 100 mhz, max f rbcck maximum readback frequency with respect to nominal cclk 60 60 60 mhz, max f mccktol frequency tolerance with respect to nominal cclk 50 50 50 % boundary-scan port timing specifications t taptck tms and tdi setup time before tck 1.0 1.0 1.0 ns, min t tcktap tms and tdi hold time after tck 2.0 2.0 2.0 ns, min t tcktdo tck falling edge to tdo output valid 6 6 6 ns, max f tck maximum configuration tck clock frequency 66 66 66 mhz, max f tckb maximum boundary-scan tck clock frequency 66 66 66 mhz, max
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 48 bpi master flash mode programming switching t bpicco (4) addr[25:0], rs[1:0], fcs_ b, foe_b, fwe_b outputs valid after cclk rising edge 10 10 10 ns t bpidcc /t bpiccd setup/hold on d[15: 0] data input pins 3.0 0.5 3.0 0.5 3.0 0.5 ns t initaddr minimum period of initia l addr[25:0] address cycles 3.0 3.0 3.0 cclk cycles spi master flash mode programming switching t spidcc /t spidccd din setup/hold before/after the rising cclk edge 4.0 0.0 4.0 0.0 5.0 0.0 ns t spiccm mosi clock to out 10 10 10 ns t spiccfc fcs_b clock to out 10 10 10 ns t fsinit /t fsinith fs[2:0] to init_b rising edge setup and hold 2 2 2 s cclk output (master modes) t mcckl master cclk clock minimum low time 3.0 3.0 3.0 ns, min t mcckh master cclk clock minimum high time 3.0 3.0 3.0 ns, min cclk input (slave modes) t scckl slave cclk clock minimum low time 2.0 2.0 2.0 ns, min t scckh slave cclk clock minimum high time 2.0 2.0 2.0 ns, min dynamic reconfiguration port (drp) for dcm and pll before and after dclk f dck maximum frequency for dclk 450 400 400 mhz t dmcck_daddr /t dmckc_daddr daddr setup/hold 1.35 0.0 1.56 0.0 1.56 0.0 ns t dmcck_di /t dmckc_di di setup/hold 1.35 0.0 1.56 0.0 1.56 0.0 ns t dmcck_den /t dmckc_den den setup/hold time 1.35 0.0 1.56 0.0 1.56 0.0 ns t dmcck_dwe /t dmckc_dwe dwe setup/hold time 1.35 0.0 1.56 0.0 1.56 0.0 ns t dmcko_do clk to out of do (3) 1.12 1.30 1.30 ns t dmcko_drdy clk to out of drdy 1.12 1.30 1.30 ns notes: 1. maximum frequency and setup/hold timing parameters are for 3.3v and 2.5v configuration voltages. 2. to support longer delays in configuration, use the design solutions described in the virtex-5 fpga user guide . 3. do will hold until next drp operation. 4. only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the i/o. ta bl e 7 0 : configuration switching characteristics (cont?d) symbol description speed grade units -2i -1i -1m
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 49 clock buffers and networks ta bl e 7 1 : global clock switching characte ristics (incl uding bufgctrl) symbol description devices speed grade units -2i -1i -1m t bccck_ce /t bcckc_ce (1) ce pins setup/hold all 0.27 0.00 0.31 0.00 0.31 0.00 ns t bccck_s /t bcckc_s (1) s pins setup/hold all 0.27 0.00 0.31 0.00 0.31 0.00 ns t bccko_o (2) bufgctrl delay from i0/i1 to o lx30t, lx85, lx110, lx110t, sx50t, fx70t, fx100t, and fx130t 0.22 0.25 0.25 ns lx155t 0.14 0.30 n/a ns lx220t, lx330t, sx95t, sx240t, and fx200t 0.22 0.25 n/a ns maximum frequency f max global clock tree (bufg) lx30t, lx85, lx110, lx110t, sx50t, and fx70t(i) 667 600 n/a mhz lx155t, fx70t(m), and fx100t 600 550 550 mhz fx130t 500 450 n/a mhz lx220t, lx330t, sx95t, sx240t, and fx200t 500 450 n/a mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glitch-free operation. the other global clock setup and h old times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis whe n switching between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. ta bl e 7 2 : input/output clock switching characteristics (bufio) symbol description speed grade units -2i -1i -1m t bufiocko_o clock to out delay from i to o 1.16 1.29 1.29 ns maximum frequency f max i/o clock tree (bufio) 710 644 644 mhz
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 50 ta bl e 7 3 : regional clock switching characteristics (bufr) symbol description devices speed grade units -2i -1i -1m t brcko_o clock to out delay from i to o lx30t, lx85, lx110, lx110t, sx50t, fx100t, and fx130t 0.59 0.67 0.67 ns fx70t 0.74 0.83 0.83 ns lx155t 0.80 0.90 n/a ns lx220t, lx330t, sx95t, sx240t, and fx200t 0.59 0.67 n/a ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set lx30t, lx85, lx110, lx110t, sx50t, fx70t, fx100t, and fx130t 0.24 0.26 0.26 ns lx155t 0.26 0.30 n/a ns lx220t, lx330t, sx95t, sx240t, and fx200t 0.24 0.26 n/a ns t brdo_clro propagation delay from clr to o all 0.70 0.82 0.82 ns maximum frequency f max regional clock tree (bufr) all 250 250 250 mhz
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 51 pll switching characteristics ta bl e 7 4 : pll specification symbol description speed grade units -2i -1i -1m f inmax maximum input clock frequency 710 645 645 mhz f inmin minimum input clock frequency 19 19 19 mhz f injitter maximum input clock period jitter <20% of clock input period or 1 ns max f induty allowable input duty cycle: 19?49 mhz 25/75 % allowable input duty cycle: 50?199 mhz 30/70 % allowable input duty cycle: 200?399 mhz 35/65 % allowable input duty cycle: 400?499 mhz 40/60 % allowable input duty cycle: >500 mhz 45/55 % f vcomin minimum pll vco frequency 400 400 400 mhz f vcomax maximum pll vco frequency 1200 1000 1000 mhz f bandwidth low pll bandwidth at typical (1) 111mhz high pll bandwidth at typical (1) 444mhz t staphaoffset static phase offset of the pll outputs 120 120 120 ps t outjitter pll output jitter (2) note 1 t outduty pll output clock duty cycle precision (3) 200 200 200 ps t lockmax pll maximum lock time (4) 100 100 100 s f outmax pll maximum output frequency for lx30t, lx85, lx110, lx110t, sx50t, and fx70t(i) devices 667 600 n/a mhz pll maximum output frequency for lx155t, fx70t(m), and fx100t devices 600 550 550 mhz pll maximum output frequency for fx130t devices 500 450 n/a mhz pll maximum output frequency for lx220t, lx330t, sx95t, sx240t, and fx200t devices 500 450 n/a mhz f outmin pll minimum output frequency (5) 3.125 3.125 3.125 mhz t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max rst minpulse minimum reset pulse width 5 5 5 ns f pfdmax maximum frequency at the phase frequency detector 500 450 450 mhz f pfdmin minimum frequency at the phase frequency detector 19 19 19 mhz t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle notes: 1. the pll does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequenc ies. 2. values for this parameter are available in the architecture wizard. 3. includes global clock buffer. 4. the lock signal must be sampled after t lockmax . the lock signal is invalid after configuration or reset until the t lockmax time has expired. 5. calculated as f vco /128 assuming output duty cycle is 50%.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 52 ta bl e 7 5 : pll in pmcd mode switching characteristics symbol description speed grade units -2i -1i -1m t pllcck_rel /t pllckc_rel rel setup and hold for all outputs 0.00 0.60 0.00 0.60 0.00 0.60 ns t pllccko maximum clock propagation delay 4.6 5.2 5.2 ns clkin_freq_max maximum input frequency 710 645 645 mhz clkin_freq_min minimum input frequency 1 1 1 mhz clkin_duty_cycle allowable input duty cycle: 1?49 mhz 25/75 % allowable input duty cycle: 50?199 mhz 30/70 % allowable input duty cycle: 200?399 mhz 35/65 % allowable input duty cycle: 400?499 mhz 40/60 % allowable input duty cycle: >500 mhz 45/55 % res_rel_pulse_min minimum pulse width for rst and rel 5 5 5 ns
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 53 dcm switching characteristics ta bl e 7 6 : operating frequency ranges for dcm in maximum speed (ms) mode symbol description speed grade units -2i -1i -1m outputs clocks (low frequency mode) f 1xlfmsmin clk0, clk90, clk180, clk270 32.00 32.00 32.00 mhz f 1xlfmsmax 135.00 120.00 120.00 mhz f 2xlfmsmin clk2x, clk2x180 64.00 64.00 64.00 mhz f 2xlfmsmax 270.00 240.00 240.00 mhz f dvlfmsmin clkdv (5) 2.0 2.0 2.0 mhz f dvlfmsmax 90.00 80.00 80.00 mhz f fxlfmsmin clkfx, clkfx180 32.00 32.00 32.00 mhz f fxlfmsmax 160.00 140.00 140.00 mhz input clocks (low frequency mode) f dlllfmsmin clkin (using dll outputs) (1)(3)(4) 32.00 32.00 32.00 mhz f dlllfmsmax 135.00 120.00 120.00 mhz f clkinlffxmsmin clkin (using dfs outputs only) (2)(3)(4) 1.00 1.00 1.00 mhz f clkinlffxmsmax 160.00 140.00 140.00 mhz f psclklfmsmin psclk 1.00 1.00 1.00 khz f psclklfmsmax 500.00 450.00 450.00 mhz outputs clocks (hig h frequency mode) f 1xhfmsmin clk0, clk90, clk180, clk270 120.00 120.00 120.00 mhz f 1xhfmsmax 500.00 450.00 450.00 mhz f 2xhfmsmin clk2x, clk2x180 240.00 240.00 240.00 mhz f 2xhfmsmax 500.00 450.00 450.00 mhz f dvhfmsmin clkdv (5) 7.5 7.5 7.5 mhz f dvhfmsmax 333.34 300.00 300.00 mhz f fxhfmsmin clkfx, clkfx180 (5) 140.00 140.00 140.00 mhz f fxhfmsmax 375.00 350.00 350.00 mhz input clocks (high frequency mode) f dllhfmsmin clkin (using dll outputs) (1)(3)(4) 120.00 120.00 120.00 mhz f dllhfmsmax 500.00 450.00 450.00 mhz f clkinhffxmsmin clkin (using dfs outputs only) (2)(3)(4)(5) 25.00 25.00 25.00 mhz f clkinhffxmsmax 375.00 350.00 350.00 mhz f psclkhfmsmin psclk 1.00 1.00 1.00 khz f psclkhfmsmax 500.00 450.00 450.00 mhz notes: 1. dll outputs are used in these instances to describe the output s: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. other resources can limit the maximum input frequency. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by_2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45). 5. only available for i-temperature conditions.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 54 ta bl e 7 7 : operating frequency ranges for dcm in maximum range (mr) mode (5) symbol description speed grade units -2i -1i -1m outputs clocks (low frequency mode) f 1xmrmin clk0, clk90, clk180, clk270 19.00 19.00 19.00 mhz f 1xmrmax 32.00 32.00 32.00 mhz f 2xmrmin clk2x, clk2x180 38.00 38.00 38.00 mhz f 2xmrmax 64.00 64.00 64.00 mhz f dllmrmin clkdv 1.19 1.19 1.19 mhz f dllmrmax 21.34 21.34 21.34 mhz f fxmrmin clkfx, clkfx180 19.00 19.00 19.00 mhz f fxmrmax 40.00 40.00 40.00 mhz input clocks (low frequency mode) f clkindllmrmin clkin (using dll outputs) (1)(3)(4) 19.00 19.00 19.00 mhz f clkindllmrmax 32.00 32.00 32.00 mhz f clkinfxmrmin clkin (using dfs outputs only) (2)(3)(4) 1.00 1.00 1.00 mhz f clkinfxmrmax 40.00 40.00 40.00 mhz f psclkmrmin psclk 1.00 1.00 1.00 khz f psclkmrmax 270.00 240.00 240.00 mhz notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. other resources can limit the maximum input frequency. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by_2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45). 5. maximum range is not available outside of i-temperature conditions.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 55 ta bl e 7 8 : input clock tolerances symbol description frequency range value units duty cycle input tolerance (in %) t dutycycrange_1 psclk only < 1 mhz 25 - 75 % t dutycycrange_1_50 psclk and clkin 1 - 50 mhz 25 - 75 % t dutycycrange_50_100 50 - 100 mhz 30 - 70 % t dutycycrange_100_200 100 - 200 mhz 40 - 60 % t dutycycrange_200_400 200 - 400 mhz (4) 45 - 55 % t dutycycrange_400 > 400 mhz 45 - 55 % input clock cycle-cycle ji tter (low frequency mode) speed grade units -2i -1i -1m t cyclfdll clkin (using dll outputs) (1) 300.00 345.00 345.00 ps t cyclffx clkin (using dfs outputs) (2) 300.00 345.00 345.00 ps input clock cycle-cycle jitter (high frequency mode) t cychfdll clkin (using dll outputs) (1) 150.00 173.00 173.00 ps t cychffx clkin (using dfs outputs) (2) 150.00 173.00 173.00 ps input clock period jitter (low frequency mode) t perlfdll clkin (using dll outputs) (1) 1.00 1.15 1.15 ns t perlffx clkin (using dfs outputs) (2) 1.00 1.15 1.15 ns input clock period jitter (high frequency mode) t perhfdll clkin (using dll outputs) (1) 1.00 1.15 1.15 ns t perhffx clkin (using dfs outputs) (2) 1.00 1.15 1.15 ns feedback clock path delay variation t clkfb_delay_var clkfb off-chip feedback 1.00 1.15 1.15 ns notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. if both dll and dfs outputs are used, follow the more restrictive specifications. 4. this duty cycle specification does not apply to the gtp_dual to dcm or gtx_dual to dcm connection. the gtp transceivers drive the dcms at the following frequencies: 320 mhz for -1i speed grade devices, or 375 mhz for -2i speed grade devices. the gtx transceiv ers drive the dcms at the following frequencies: 450 mhz for -1i speed grade devices or 500 mhz for -2i speed grade devices.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 56 output clock jitter output clock phase alignment ta bl e 7 9 : output clock jitter symbol description speed grade units -2i -1i -1m clock synthesis period jitter t perjitt_0 clk0 120 120 120 ps t perjitt_90 clk90 120120120ps t perjitt_180 clk180 120 120 120 ps t perjitt_270 clk270 120 120 120 ps t perjitt_2x clk2x, clk2x180 200 230 230 ps t perjitt_dv1 clkdv (integer division) 150 180 180 ps t perjitt_dv2 clkdv (non-integer division) 300 345 345 ps t perjitt_fx clkfx, clkfx180 note 1 note 1 note 1 ps notes: 1. values for this parameter are available in the architecture wizard. ta bl e 8 0 : output clock phase alignment symbol description speed grade units -2i -1i -1m phase offset betwee n clkin an d clkfb t in_fb_offset clkin/clkfb 50 60 60 ps phase offset between any dcm outputs (1) t out_offset_1x clk0, clk90, clk180, clk270 140 160 160 ps t out_offset_2x clk2x, clk2x180, clkdv 150 200 200 ps t out_offset_fx clkfx, clkfx180 160 220 220 ps duty cycle precision (2) t duty_cyc_dll dll outputs (3) 150 180 180 ps t duty_cyc_fx dfs outputs (4) 150 180 180 ps notes: 1. all phase offsets are with respect to group clk1x. 2. clkout_duty_cycle_dll applies to the 1x clock outputs (clk0, clk90, clk 180, and clk270) only if duty_cycle_correctio n = true. the duty cycle distortion includes the global clock tree (bufg). 3. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 4. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 57 ta bl e 8 1 : miscellaneous timing parameters symbol description speed grade units -2i -1i -1m time required to achieve lock t dll_240 dll output ? frequency range > 240 mhz (1) 80.00 80.00 80.00 s t dll_120_240 dll output ? frequency range 120 - 240 mhz (1) 250.00 250.00 250.00 s t dll_60_120 dll output ? frequency range 60 - 120 mhz (1) 900.00 900.00 900.00 s t dll_50_60 dll output ? frequency range 50 - 60 mhz (1) 1300.00 1300.00 1300.00 s t dll_40_50 dll output ? frequency range 40 - 50 mhz (1) 2000.00 2000.00 2000.00 s t dll_30_40 dll output ? frequency range 30 - 40 mhz (1) 3600.00 3600.00 3600.00 s t dll_24_30 dll output ? frequency range 24 - 30 mhz (1) 5000.00 5000.00 5000.00 s t dll_30 dll output ? frequency range < 30 mhz (1) 5000.00 5000.00 5000.00 s t fx_min dfs outputs (2) 10.00 10.00 10.00 ms t fx_max 10.00 10.00 10.00 ms t dll_fine_shift multiplication factor for dll lock time with fine shift 2.00 2.00 2.00 fine phase shifting t range_ms absolute shifting range in maximum speed mode 7.00 7.00 7.00 ns t range_mr (3) absolute shifting range in maximum range mode 10.00 10.00 10.00 ns delay lines t tap_ms_min tap delay resolution (min) in maximum speed mode 7.00 7.00 7.00 ps t tap_ms_max tap delay resolution (max) in maximum speed mode 30.00 30.00 30.00 ps t tap_mr_min (3) tap delay resolution (min) in maximum range mode 10.00 10.00 10.00 ps t tap_mr_max (3) tap delay resolution (max) in maximum range mode 40.00 40.00 40.00 ps notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. maximum range is not available outside of i-temperature conditions. ta bl e 8 2 : frequency synthesis attribute min max clkfx_multiply 2 33 clkfx_divide 1 32 ta bl e 8 3 : dcm switching characteristics symbol description speed grade units -2i -1i -1m t dmcck_psen / t dmckc_psen psen setup/hold 1.35 0.00 1.56 0.00 1.56 0.00 ns t dmcck_psincdec / t dmckc_psincdec psincdec setup/hold 1.35 0.00 1.56 0.00 1.56 0.00 ns t dmcko_psdone clock to out of psdone 1.12 1.30 1.30 ns
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 58 virtex-5q device pin-to-pin output parame ter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 8 4 . values are expressed in nanoseconds unless otherwise noted. ta bl e 8 4 : global clock input to output delay without dcm or pll symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, without dcm or pll t ickof global clock and outff without dcm or pll xq5vlx30t 6.04 6.73 n/a ns xq5vlx85 6.28 6.99 n/a ns xq5vlx110 6.35 7.06 n/a ns xq5vlx110t 6.35 7.06 n/a ns xq5vlx155t 6.68 7.52 n/a ns xq5vlx220t 6.99 7.71 n/a ns xq5vlx330t n/a 7.91 n/a ns xq5vsx50t 6.27 6.97 n/a ns xq5vsx95t 6.59 7.30 n/a ns xq5vsx240t n/a 7.98 n/a ns xq5vfx70t 6.33 7.04 7.04 ns xq5vfx100t 6.73 7.44 7.44 ns xq5vfx130t 6.80 7.52 n/a ns xq5vfx200t n/a 7.91 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 59 ta bl e 8 5 : global clock input to output delay with dcm in system-synchronous mode symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with dcm in system-synchronous mode t ickofdcm global clock and outff with dcm xq5vlx30t 2.56 2.93 n/a ns xq5vlx85 2.63 3.00 n/a ns xq5vlx110 2.69 3.06 n/a ns xq5vlx110t 2.69 3.06 n/a ns xq5vlx155t 2.74 3.10 n/a ns xq5vlx220t 2.83 3.18 n/a ns xq5vlx330t n/a 3.37 n/a ns xq5vsx50t 2.69 3.05 n/a ns xq5vsx95t 2.64 3.00 n/a ns xq5vsx240t n/a 3.36 n/a ns xq5vfx70t 2.74 3.12 3.12 ns xq5vfx100t 2.59 3.00 3.00 ns xq5vfx130t 2.67 3.07 n/a ns xq5vfx200t n/a 3.27 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already included in the timing calculation.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 60 ta bl e 8 6 : global clock input to output delay with dcm in source-synchronous mode symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with dcm in source-synchronous mode t ickofdcm_0 global clock and outff with dcm xq5vlx30t 3.71 4.15 n/a ns xq5vlx85 3.86 4.29 n/a ns xq5vlx110 3.92 4.36 n/a ns xq5vlx110t 3.92 4.36 n/a ns xq5vlx155t 4.18 4.62 n/a ns xq5vlx220t 4.41 4.85 n/a ns xq5vlx330t n/a 5.04 n/a ns xq5vsx50t 3.91 4.35 n/a ns xq5vsx95t 4.16 4.59 n/a ns xq5vsx240t n/a 5.11 n/a ns xq5vfx70t 3.96 4.41 4.41 ns xq5vfx100t4.104.534.53ns xq5vfx130t 4.29 4.74 n/a ns xq5vfx200t n/a 5.03 n/a ns notes: 1. list ed above are representative values where one global clock input drives one vertical clock line in each accessible column, and w here all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already included in the timing calculation.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 61 ta bl e 8 7 : global clock input to output delay with pll in system-synchronous mode symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with pll in system-synchronous mode t ickofpll global clock and outff with pll xq5vlx30t 2.30 2.70 n/a ns xq5vlx85 2.49 2.88 n/a ns xq5vlx110 2.53 2.92 n/a ns xq5vlx110t 2.53 2.92 n/a ns xq5vlx155t 2.60 3.01 n/a ns xq5vlx220t 2.74 3.12 n/a ns xq5vlx330t n/a 3.27 n/a ns xq5vsx50t 2.36 2.76 n/a ns xq5vsx95t 2.29 2.69 n/a ns xq5vsx240t n/a 3.34 n/a ns xq5vfx70t 2.71 3.10 3.10 ns xq5vfx100t2.703.103.10ns xq5vfx130t 2.75 3.17 n/a ns xq5vfx200t n/a 3.35 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is included in the timing calculation.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 62 ta bl e 8 8 : global clock input to output delay with pll in source-synchronous mode symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with pll in source-synchronous mode t ickofpll_0 global clock and outff with pll xq5vlx30t 4.32 4.82 n/a ns xq5vlx85 4.40 4.88 n/a ns xq5vlx110 4.44 4.92 n/a ns xq5vlx110t 4.44 4.92 n/a ns xq5vlx155t 4.66 5.16 n/a ns xq5vlx220t 4.85 5.29 n/a ns xq5vlx330t n/a 5.44 n/a ns xq5vsx50t 4.54 5.02 n/a ns xq5vsx95t 4.68 5.14 n/a ns xq5vsx240t n/a 5.51 n/a ns xq5vfx70t 4.54 5.02 5.02 ns xq5vfx100t4.705.195.19ns xq5vfx130t 4.86 5.40 n/a ns xq5vfx200t n/a 5.55 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is included in the timing calculation.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 63 ta bl e 8 9 : global clock input to output delay with dcm and pll in system-synchronous mode symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with dcm and pll in system-synchronous mode t ickofdcm_pll global clock and outff with dcm and pll xq5vlx30t 2.48 2.84 n/a ns xq5vlx85 2.55 2.91 n/a ns xq5vlx110 2.61 2.97 n/a ns xq5vlx110t 2.61 2.97 n/a ns xq5vlx155t 2.66 3.01 n/a ns xq5vlx220t 2.75 3.09 n/a ns xq5vlx330t n/a 3.28 n/a ns xq5vsx50t 2.61 2.96 n/a ns xq5vsx95t 2.56 2.91 n/a ns xq5vsx240t n/a 3.27 n/a ns xq5vfx70t 2.66 3.03 3.03 ns xq5vfx100t 2.51 2.91 2.91 ns xq5vfx130t 2.59 2.98 n/a ns xq5vfx200t n/a 3.18 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm and pll output jitter are already included in the timing calculation.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 64 ta bl e 9 0 : global clock input to output delay with dcm and pll in source-synchronous mode symbol description device speed grade units -2i -1i -1m lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with dcm and pll in source-synchronous mode t ickofdcm0_pll global clock and outff with dcm and pll xq5vlx30t 3.63 4.06 n/a ns xq5vlx85 3.78 4.20 n/a ns xq5vlx110 3.84 4.27 n/a ns xq5vlx110t 3.84 4.27 n/a ns xq5vlx155t 4.10 4.53 n/a ns xq5vlx220t 4.33 4.76 n/a ns xq5vlx330t n/a 4.95 n/a ns xq5vsx50t 3.83 4.26 n/a ns xq5vsx95t 4.08 4.50 n/a ns xq5vsx240t n/a 5.02 n/a ns xq5vfx70t 3.88 4.32 4.32 ns xq5vfx100t 4.02 4.44 4.44 ns xq5vfx130t 4.21 4.65 n/a ns xq5vfx200t n/a 4.94 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm and pll output jitter are already included in the timing calculation.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 65 virtex-5q device pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 9 1 . values are expressed in nanoseconds unless otherwise noted. ta bl e 9 1 : global clock setup and hold without dcm or pll symbol description device speed grade units -2i -1i -1m input setup and hold time relative to glob al clock input signal for lvcmos25 standard (1) t psfd / t phfd full delay (legacy delay or default delay) global clock and iff (2) without dcm or pll xq5vlx30t 1.60 ?0.35 1.76 ?0.35 n/a ns xq5vlx85 1.89 ?0.49 2.09 ?0.49 n/a ns xq5vlx110 1.88 ?0.43 2.09 ?0.43 n/a ns xq5vlx110t 1.88 ?0.43 2.09 ?0.43 n/a ns xq5vlx155t 2.36 ?0.50 2.78 ?0.49 n/a ns xq5vlx220t 2.57 ?0.74 2.86 ?0.74 n/a ns xq5vlx330t n/a 2.86 ?0.56 n/a ns xq5vsx50t 1.74 ?0.31 1.93 ?0.31 n/a ns xq5vsx95t 2.10 ?0.44 2.32 ?0.44 n/a ns xq5vsx240t n/a 2.28 0.18 n/a ns xq5vfx70t 2.06 ?0.30 2.35 ?0.30 2.35 ?0.30 ns xq5vfx100t 2.38 ?0.42 2.66 ?0.42 2.66 ?0.42 ns xq5vfx130t 2.59 ?0.54 2.95 ?0.54 n/a ns xq5vfx200t n/a 2.81 ?0.43 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 66 ta bl e 9 2 : global clock setup and hold with dcm in system-synchronous mode symbol description device speed grade units -2i -1i -1m input setup and hold time relative to glob al clock input signal for lvcmos25 standard (1) t psdcm / t phdcm no delay global clock and iff (2) with dcm in system-synchronous mode xq5vlx30t 1.70 ?0.50 1.88 ?0.50 n/a ns xq5vlx85 1.76 ?0.43 1.95 ?0.43 n/a ns xq5vlx110 1.76 ?0.37 1.95 ?0.37 n/a ns xq5vlx110t 1.76 ?0.37 1.95 ?0.37 n/a ns xq5vlx155t 2.16 ?0.32 2.38 ?0.32 n/a ns xq5vlx220t 2.17 ?0.27 2.44 ?0.27 n/a ns xq5vlx330t n/a 2.44 ?0.10 n/a ns xq5vsx50t 1.76 ?0.37 1.95 ?0.37 n/a ns xq5vsx95t 2.34 ?0.41 2.35 ?0.41 n/a ns xq5vsx240t n/a 2.54 ?0.10 n/a ns xq5vfx70t 1.86 ?0.36 1.98 ?0.36 1.98 ?0.36 ns xq5vfx100t 2.35 ?0.51 2.49 ?0.49 2.49 ?0.49 ns xq5vfx130t 2.48 ?0.43 2.72 ?0.42 n/a ns xq5vfx200t n/a 2.43 ?0.21 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include dcm clk0 jitt er. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 67 ta bl e 9 3 : global clock setup and hold with dcm in source-synchronous mode symbol description device speed grade units -2i -1i -1m input setup and hold time relative to glob al clock input signal for lvcmos25 standard (1) t psdcm0 / t phdcm0 no delay global clock and iff (2) with dcm in source-synchronous mode xq5vlx30t 0.27 0.62 0.27 0.66 n/a ns xq5vlx85 0.24 0.76 0.24 0.80 n/a ns xq5vlx110 0.24 0.82 0.24 0.87 n/a ns xq5vlx110t 0.24 0.82 0.24 0.87 n/a ns xq5vlx155t 0.14 1.08 0.16 1.13 n/a ns xq5vlx220t 0.21 1.31 0.22 1.36 n/a ns xq5vlx330t n/a 0.22 1.55 n/a ns xq5vsx50t 0.25 0.82 0.25 0.86 n/a ns xq5vsx95t 0.24 1.06 0.24 1.11 n/a ns xq5vsx240t n/a 0.21 1.62 n/a ns xq5vfx70t 0.14 0.86 0.14 0.92 0.14 0.92 ns xq5vfx100t 0.21 1.00 0.21 1.05 0.21 1.05 ns xq5vfx130t 0.21 1.19 0.24 1.25 n/a ns xq5vfx200t n/a 0.16 1.55 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include dcm clk0 jitt er. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 68 ta bl e 9 4 : global clock setup and hold with pll in system-synchronous mode symbol description device speed grade units -2i -1i -1m input setup and hold time relative to glob al clock input signal for lvcmos25 standard (1) t pspll / t phpll no delay global clock and iff (2) with pll in system-synchronous mode xq5vlx30t 1.68 ?0.80 1.90 ?0.79 n/a ns xq5vlx85 1.95 ?0.62 2.09 ?0.61 n/a ns xq5vlx110 1.96 ?0.57 2.10 ?0.57 n/a ns xq5vlx110t 1.96 ?0.57 2.10 ?0.57 n/a ns xq5vlx155t 2.09 ?0.49 2.37 ?0.47 n/a ns xq5vlx220t 1.93 ?0.36 2.09 ?0.36 n/a ns xq5vlx330t n/a 2.34 ?0.21 n/a ns xq5vsx50t 2.07 ?0.72 2.20 ?0.72 n/a ns xq5vsx95t 2.17 ?0.80 2.35 ?0.79 n/a ns xq5vsx240t n/a 2.33 ?0.14 n/a ns xq5vfx70t 1.90 ?0.30 2.07 ?0.30 2.07 ?0.30 ns xq5vfx100t 1.91 ?0.40 2.09 ?0.38 2.09 ?0.38 ns xq5vfx130t 1.95 ?0.28 2.14 ?0.24 n/a ns xq5vfx200t n/a 2.29 ?0.14 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include pll clkout0 j itter. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 69 ta bl e 9 5 : global clock setup and hold with pll in source-synchronous mode symbol description device speed grade units -2i -1i -1m input setup and hold time relative to glob al clock input signal for lvcmos25 standard (1) t pspll0 / t phpll0 no delay global clock and iff (2) with pll in source-synchronous mode xq5vlx30t ?0.33 1.22 ?0.33 1.34 n/a ns xq5vlx85 ?0.23 1.30 ?0.22 1.39 n/a ns xq5vlx110 ?0.24 1.34 ?0.23 1.43 n/a ns xq5vlx110t ?0.25 1.34 ?0.23 1.43 n/a ns xq5vlx155t ?0.12 1.56 ?0.10 1.67 n/a ns xq5vlx220t ?0.34 1.75 ?0.30 1.80 n/a ns xq5vlx330t n/a ?0.30 1.95 n/a ns xq5vsx50t ?0.26 1.44 ?0.25 1.53 n/a ns xq5vsx95t ?0.26 1.58 ?0.24 1.65 n/a ns xq5vsx240t n/a ?0.31 2.02 n/a ns xq5vfx70t ?0.10 1.44 ?0.09 1.53 ?0.09 1.53 ns xq5vfx100t ?0.18 1.60 ?0.18 1.71 ?0.18 1.71 ns xq5vfx130t ?0.11 1.76 ?0.09 1.92 n/a ns xq5vfx200t n/a ?0.10 2.06 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include pll clkout0 j itter. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 70 ta bl e 9 6 : global clock setup and hold with dcm and pll in system-synchronous mode symbol description device speed grade units -2i -1i -1m input setup and hold time relative to glob al clock input signal for lvcmos25 standard (1) t psdcmpll / t phdcmpll no delay global clock and iff (2) with dcm and pll in system-synchronous mode xq5vlx30t 1.89 ?0.58 2.06 ?0.58 n/a ns xq5vlx85 1.93 ?0.51 2.13 ?0.51 n/a ns xq5vlx110 1.93 ?0.45 2.13 ?0.45 n/a ns xq5vlx110t 1.93 ?0.45 2.13 ?0.45 n/a ns xq5vlx155t 2.31 ?0.40 2.55 ?0.40 n/a ns xq5vlx220t 2.32 ?0.35 2.61 ?0.35 n/a ns xq5vlx330t n/a 2.61 ?0.18 n/a ns xq5vsx50t 1.94 ?0.45 2.14 ?0.45 n/a ns xq5vsx95t 2.51 ?0.49 2.53 ?0.49 n/a ns xq5vsx240t n/a 2.70 ?0.18 n/a ns xq5vfx70t 2.03 ?0.44 2.16 ?0.44 2.16 ?0.44 ns xq5vfx100t 2.51 ?0.59 2.66 ?0.58 2.66 ?0.58 ns xq5vfx130t 2.64 ?0.51 2.89 ?0.51 n/a ns xq5vfx200t n/a 2.59 ?0.30 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include cmt jitter; d cm clk0 driving pll, pll clkout0 driving bufg. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 71 ta bl e 9 7 : global clock setup and hold with dcm and pll in source-synchronous mode symbol description device speed grade units - 2i - 1i -1m example data input setup and hold times relative to a forwarded clock input pin, (1) using dcm, pll, and global clock buffer. for situations where clock and data inputs conform to different st andards, adjust the setup and hold values accordingly using the v alues shown in iob switching characteristics . t psdcmpll_0 / t phdcmpll_0 no delay global clock and iff (2) with dcm and pll in source-synchronous mode xq5vlx30t 0.46 0.54 0.46 0.57 n/a ns xq5vlx85 0.42 0.68 0.42 0.71 n/a ns xq5vlx110 0.41 0.74 0.41 0.78 n/a ns xq5vlx110t 0.41 0.74 0.41 0.78 n/a ns xq5vlx155t 0.29 1.00 0.33 1.04 n/a ns xq5vlx220t 0.36 1.23 0.38 1.27 n/a ns xq5vlx330t n/a 0.38 1.46 n/a ns xq5vsx50t 0.43 0.74 0.43 0.77 n/a ns xq5vsx95t 0.41 0.98 0.41 1.02 n/a ns xq5vsx240t n/a 0.38 1.53 n/a ns xq5vfx70t 0.32 0.78 0.32 0.83 0.32 0.83 ns xq5vfx100t 0.35 0.92 0.35 0.96 0.35 0.96 ns xq5vfx130t 0.37 1.11 0.41 1.16 n/a ns xq5vfx200t n/a 0.33 1.46 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. the timing values were measured using th e fine-phase adjustment feature of the dcm. these measurements include cmt jitter; dcm clk0 driving pll, pll clkout0 driving bufg. package skew is not included in these measurements. 2. iff = input flip-flop
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 72 source-synchronous switching characteristics the parameters in this section provide the necessary values for calculating timing budgets for virtex-5q fpga source- synchronous transmitter and receiver data-valid windows. ta bl e 9 8 : duty cycle distortion and clock-tree skew symbol description device speed grade units -2i -1i -1m t dcd_clk global clock tree du ty cycle distortion (1) all 0.120.120.12ns t ckskew global clock tree skew (2) xq5vlx30t 0.22 0.22 n/a ns xq5vlx85 0.43 0.45 n/a ns xq5vlx110 0.50 0.51 n/a ns xq5vlx110t 0.50 0.51 n/a ns xq5vlx155t 0.85 0.88 n/a ns xq5vlx220t 1.07 1.10 n/a ns xq5vlx330t n/a 1.29 n/a ns xq5vsx50t 0.44 0.45 n/a ns xq5vsx95t 0.72 0.74 n/a ns xq5vsx240t n/a 1.36 n/a ns xq5vfx70t 0.420.430.43ns xq5vfx100t 0.84 0.86 0.86 ns xq5vfx130t 0.84 0.86 n/a ns xq5vfx200t n/a 1.29 n/a ns t dcd_bufio i/o clock tree duty cycle distortion all 0.10 0.10 0.10 ns t bufioskew i/o clock tree skew across one clock region all 0.07 0.08 0.08 ns t dcd_bufr regional clock tree duty cycle distortion all 0.25 0.25 0.25 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to your application.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 73 ta bl e 9 9 : package skew (1) symbol description device package value units t pkgskew package skew (2) xq5vlx30t (3) ff323 127 ps xq5vlx85 ef676 142 ps xq5vlx110 ef676 142 ps xq5vlx110 ef1153 173 ps xq5vlx110t ef1136 163 ps xq5vlx155t ef1136 147 ps xq5vlx220t ef1738 156 ps xq5vlx330t ef1738 155 ps xq5vsx50t ef665 103 ps xq5vsx95t ef1136 176 ps xq5vsx240t (3) ff1738 161 ps xq5vfx70t ef665 102 ps xq5vfx70t ef1136 153 ps xq5vfx100t ef1136 144 ps xq5vfx100t ef1738 172 ps xq5vfx130t ef1738 181 ps xq5vfx200t (3) ff1738 164 ps notes: 1. package trace length information is available for these device/package combinations. this information can be used to deskew t he package. 2. these values represent the worst-case skew between any two selectio resources in the package: shortest flight time to longest flight time from pad to ball (7.0 ps per mm). 3. the ef package is not available for these devices. table 100: sample window symbol description device speed grade units -2i -1i -1m t samp sampling error at receiver pins (1) all 500 550 550 ps t samp_bufio sampling error at receiver pins using bufio (2) all 400 450 450 ps notes: 1. this parameter indicates the total sampling error of virtex-5q fpga ddr input registers across voltage, temperature, and proc ess. the characterization methodology uses the dcm to capture the ddr input registers? edges of operation. these measurements include: - clk0 dcm jitter - dcm accuracy (phase offset) - dcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of virtex-5q fpga ddr input registers across voltage, temperature, and proc ess. the characterization methodology uses the bufi o clock network and iodelay to capture th e ddr input registers? edges of operation. t hese measurements do not include package or clock tree skew.
virtex-5q fpga data sheet: dc and switching characteristics ds714 (v2.2) january 17, 2011 www.xilinx.com product specification 74 revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. xilinx products (including hardware, software and/or ip cores) are no t designed or intended to be fail- safe, or for use in any application requiring fail-s afe performance, such as in life-support or safety devices or systems, class iii medical devices, nuclea r facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury or severe property or environmental damage (individually and collectivel y, ?critical applications?). furthermore, xilinx products are not designed or intended for use in an y applications that affect control of a vehicle or aircraft, unless there is a fail-saf e or redundancy feature (which do es not include use of software in the xilinx device to implement the redundancy) and a warning signal upon failure to the operator. customer agrees, prior to using or distributing any systems that incorporate xilinx products, to thoroughly test the same for safety purposes. to the maximum extent permitted by applicable law, customer assumes the sole risk and liability of any use of xilinx products in critical applications. table 101: source-synchronous pin-to-pin setup/hold and clock-to-out symbol description speed grade units -2i -1i -1m data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock ?0.54 1.72 ?0.54 1.91 ?0.54 1.91 ns pin-to-pin clock-to-out using bufio t ickofcs clock-to-out of i/o clock 4.82 5.40 5.40 ns date version description of revisions 05/05/09 1.0 initial xilinx release. 12/17/09 2.0 changed the document classification from prelim inary product specification to product specification. updated xq5vsx240t, xq5vfx70t, and xq5vfx200t to production devices in ta b l e 5 4 and ta b l e 5 5 . updated package information fo r xq5vfx200t and xq5vsx240t in ta b l e 9 9 . 07/23/10 2.1 production release of xq5v fx70t and xq5vfx100t in the -1m speed grade. this includes changes to ta b l e 5 4 and ta b l e 5 5 . added a -1m column to any table with speed grades. also updated the -2i speed grade software in ta bl e 5 5 for the xq5vlx220t and xq5vsx95t device. added -1(m) column to ta bl e 4 including values for xq5vfx70t and xq5vfx100t. revised maximum v od in ta b l e 8 . updated both minimum and maximum v ocm in ta bl e 1 0 . updated minimum dv ppin in ta b l e 4 0 . in ta b l e 4 6 , updated t j4.25 and added note 5. in ta b l e 5 1 , added i-grade and m- grade delineation for gain error, bipolar gain error, and adcclk revised a idd maximum specification. added note 1 to ta bl e 5 7 . in ta bl e 7 1 , added the fx70t (m) specification for the global clock tree (bufg) f max . added the fx70t (m) specification for the f outmax to ta bl e 7 4 . added note 5 to ta b l e 7 6 . added note 5 to ta b l e 7 7 . added note 3 to ta bl e 8 1 . 01/17/11 2.2 revised production release of the xq5vfx70 t and xq5vfx100t in the -1m speed grade to software version ise 12.4 using the v1.71 speed specification (see ta bl e 5 5 ).

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